In read leveling, the interface must work with a known reference data pattern stored in memory. The DDR3 specification provides a mechanism for storing the reference pattern in a special multipurpose register (MPR). When the MPR is active, its signals replace the DQ, data mask (DM), and data strobe (DQS) signals that would otherwise come from the memory array. Writing to the MPR in preparation for read leveling can occur at a reduced transfer rate so uncalibrated timing isn’t a concern.
A typical mechanism for implementing read leveling can adjustably delay the DQS and individual DQ signals arriving from memory (Fig. 3). The memory interface then uses the delayed DQS to clock each double-rate DQ into two data bits at half speed so a second stage can capture and align with the system clock for backend processing. The goal of the leveling process is to select a delay value for DQS that maximizes the timing margins for the double-rate clocking step.
At the data rates supported by DDR3, though, simply adjusting DQS may not provide enough timing margin because skew among the individual bits in a data group can be major fractions of the timing period (Fig. 4a). Ideally, the interface’s leveling process would also be able to determine and implement delays for each data bit as well as the DQS that will center the data on DQS (Fig. 4b). This would maximize the timing margins for the double-rate clocking step. It would also ease layout by compensating for traveltime variations.
A calibration process that will achieve this centering calls for the memory controller to sweep the DQS delay through its range one step at a time. For each DQS delay step, the controller would capture a read data pattern and compare it to the expected pattern, noting which bits pass or fail at each step.
When the sweep is complete, the controller has information on the range of DQS values for which each bit line performs correctly. This gives the controller enough information to select a DQS delay value. By adjusting the delay on each data bit, the controller can then shift that bit’s operational timing range to center on the delayed DQS signal. This process maximizes the timing margins on all of the bits.
Tracking VT Variations
The read and write leveling processes occur only once, during power-up initialization of the memory interface. During normal circuit operation, however, voltage and temperature (VT) variations can alter signal timing within the memory interface device by a significant fraction of the DDR3 data rate period. To keep timing robust, then, the memory interface should also compensate for these VT variations.
One way to accomplish this is to have a test pathway in the interface that mimics the data pathways and calibrates that mimic path timing against a reference clock during initialization. By periodically checking the mimic path timing, the memory controller can determine the amount and direction of any timing shifts and apply an appropriate compensation to the memory interface signals.
Among the timing adjustments the memory interface must make is an option to control the impedance of circuits. The DDR3 specification provides a ZQ pin on the memory device as an attachment point for an impedance reference. The memory can use this reference to calibrate its own I/O impedances and present that information to the memory controller. The controller can then actively alter the memory’s ODT along with its own I/O impedances to maintain a good match among all of the circuit elements (Fig. 5).
The presence of all these calibrations and other dynamic adjustments in the memory interface—as well as the complexities of managing the activation of banks and precharge of rows, controlling memory mapping, and providing dynamic command sequencing to the memory array—makes the full design of a DDR3 memory interface a daunting task. For many developers, then, acquiring a DDR3 interface in the form of silicon IP will be the preferred path.
Such DDR3 interface IP is becoming increasingly available. Among FPGA providers, for instance, Altera and Xilinx offer reference designs that leverage their devices’ strengths to provide all of the required functionality. ASIC cores that chip designers can incorporate also are available from Rambus, Virage Logic, and others.
Design teams making an IP selection, though, will need to consider a variety of factors. One is the IP’s flexibility for adapting to specific system requirements. Flexibility may be important, for instance, in slew rate and output driver strength control, as is available in the Rambus and Virage Logic DDR3 IP. Signal slew rate directly impacts noise levels and power consumption as well as setting attainable performance limits. It may be useful in systems that don’t meed the highest performance in their memory access to be able to scale back clock speed and slew rate to save power and reduce noise.
IP Flexibility Is Key
The ability to control drive strength permits developers to readily adapt the IP for the various load levels. A high drive allows the interface to maintain signal speeds for heavy loads while a lower drive helps minimize power demand with light loading. A wide range of options, such as the nine settings from 30- to 240-O drive strengths offered by Virage Logic, makes implementing the right strength for a specific installation easier.
Above and beyond the technical specifications of the IP, however, developers should consider the business aspects of working with a supplier. A vendor’s ability to provide support can be essential to meeting market windows. The size and financial strength of the vendor can also be key in assuring customers that the vendor will survive to continue offering support.
And then there’s the issue of cost. For now, DDR3 memory devices and the interface to support them are more expensive than DDR2. But an increase in one aspect of a system design effort may generate savings in another. Looking carefully at the performance increase, power reduction, and board design simplification that DDR3 SDRAM can bring to a system may be enough to tip the balance and encourage a move up to DDR3.