Shrinking feature dimensions used in chipmanufacturing processes continue to
push the complexity and density of the circuits to groundbreaking levels. But
getting there comes with a heftier price tag when developing and fabricating
high-end application-specific ICs (ASICs).
In fact, most research analysts agree that at the 90-nm process node, taking
a cell-based ASIC from concept to production will run between $10 million and
$15 million. Plus, when designs migrate to the 65-nm node, the overall development
cost approaches $20 million.
Of course, for designs that don't push the edge on performance or complexity, processes that employ minimum features of 110, 130, or larger can deliver designs for considerably less. The lower costs result from several factors—masks are less expensive, chip complexities are typically lower, and thus the design-verification cost will drop.
Once a design is complete, it often becomes necessary to migrate to a higher-performance or more economical process. To this end, many ASIC vendors possess cell libraries that span different process nodes. Transitioning to the next process node may require considerable effort to re-verify the design, though (see "Process Migration For IP And ASICs," p. 61).
One major advantage that cell-based ASICS have over other-ASIC solutions is
the ability to combine analog and digital functions on the chip, creating a
true single-chip system. Today's mixed-signal ASIC processes can deliver RF
front ends, analog-to-digital and digital-to-analog converters, voltage references,
and many other functions not offered as standard features on the new platform
and structured ASICs or on most field-programmable gate arrays (FPGAs).
With a broader mix of on-chip functions available for cellbased ASICs, designers can craft chips for applications that range from wireless communications, networking, and computing to industrial and consumer systems. To design such systems-on-a-chip (SoCs), general-purpose electronic-designautomation (EDA) tools can be assembled into a design-flow suite that starts with design capture and goes through final layout and verification.
Still, selecting the proper tools for a particular application segment can pose a significant challenge. One approach offered by Cadence Design Systems creates application-specific collections of tools that target specific market segments. Such design kits supply a proven design flow and a set of tools selected to meet the needs of that market segment (see "Streamlining The ASIC Design Process" online at www. elecdesign.com, Drill Deeper 11342).
PLATFORM/STRUCTURED NICHE The market niche formed by the latest platform
and structured array offerings provide designers with a lower-cost alternative
to full cell-based ASICs. But platform and structured solutions tend to be digital-only
implementations. They carry limited mixed-signal functionality in the form of
phase-locked loops (PLLs), high-speed serial interfaces, and serializer/deserializer
(SERDES) channels.
Standard pre-defined chips from platform and structured ASIC vendors cut development costs by trimming mask costs, as well as the time and cost to verify a significant portion of the system logic. Trimming development costs is, of course, paramount among designers. It has established a significant market niche for the platform and structured solutions.
These solutions attack the problem by offering a fixed set of resources prefabricated in the silicon. Designers then need to only overlay their logic and define from one to five metal wiring layers to configure the logic.
Platform and structured ASICs are similar in basic concepts. They both have an internal array of logic cells with dedicated memory blocks distributed in the logic fabric, and a ring of I/O cells surrounds that fabric.
Platform ASICs tend to be more feature-rich, packing multiple PLLs, multigigabit
SERDES I/O channels, and higher gate densities than structured ASICs. A simple
automotive analogy might classify a structured ASIC as a basic sedan, while
a platform ASIC might be categorized as a luxury vehicle.
The up-front design costs for a multimegagate chip ( defining the circuit, implementing the various logic blocks, synthesizing the logic, and placing and routing the design) don't differ much from process node to process node (130 to 110, or 110 to 90 nm). Yet significant cost differences will crop up in the back-end portion of the design (design verification, timing closure, and mask creation).
In full cell-based ASIC designs, all cells are implemented from the base silicon
levels through final metallization. A complete chip analysis (timing, design-rule
checks, design verification, etc.) then must be done prior to mask creation.
With platform and structured devices, the silicon can be preverified. Many of
the library building blocks also can be preverified, reducing the back-end effort
and speeding the time to fabrication.