Troubleshoot High-Speed Buses By Clearing "Clock Scheme Fog"

SOURCE-SYNCHRONOUS PYRAMID
Although it has several more steps than the modes discussed earlier, a dedicated source-synchronous mode makes the setup process straightforward. These steps can be viewed as a setup "pyramid" consisting of successive layers of configuration choices (Fig. 4). The steps are numbered in the order in which they are normally performed. Let's follow the process from "bottom to top."

1. Assign Edge Detectors: Every synchronous digital system requires a clock. Source-synchronous systems also use one or more strobe signals. The logic analyzer implements edge detectors to mark the passing of such events. Four edge detectors are available per module, with rising and falling edges assigned independently from one another. Linking the strobe signal to a detector completes the logic analyzer's definition of when a cycle's data is valid.
2. Bind Edge Detectors Into Clock Groups: A clock group consists of one or more of the previously defined edge detectors. In turn, the clock group defines exactly which edges are needed to complete an event.
3. Define Sample Clocks: The validity of SUT operations, such as Read or Write, are determined by Boolean conditions that encompass several signals. Setting up the sample clocks prepares the logic analyzer to sample according to these Boolean equations. Just as the clock groups are made up of edge detectors, the sample clocks consist of clock groups related by various Boolean OR and AND invocations using qualifier signals.
4. Setup Group Clocking: The group clocking setup step is the point at which all of the previous definitions—edge detectors, clock groups, and sample clocks—converge. The group clocking menu also imposes timing parameters on all of the logical conditions programmed so far.
5. Define Probe Demultiplexing: Probe demultiplexing tells the logic analyzer which groups to demultiplex so that they're consistent with the source-synchronous acquisition. The logic analyzer has default mappings for various levels of demultiplexing, which are satisfactory for source-synchronous acquisitions. Therefore, this setup step simply specifies the default map. Figure 5 shows the result of a source-synchronous acquisition. Here, the strobe latches data on its rising edge. This data is then resynchronized to the master clock, as shown in the waveform view.

To increase the data throughput in digital systems, innovative data-transfer techniques are gaining popularity. These include increasing the basic clock and data speed, sending the data differentially, reducing the signal amplitude, transferring data multiple times in one clock cycle, and sending the data in a source-synchronous format.

When capturing the digital data from the buses implementing these transfer attributes, it's necessary to use an advanced logic-analysis tool that can capture these types of buses without the need for a front end "preprocessor" to manipulate-and possibly distort the data.

A new generation of logic-analyzer modules is rising to meet this need. These tools can handle high-speed synchronous clocks and capture multiplexed bus data and source-synchronous data transfers.

SOURCE-SYNCHRONOUS PYRAMID
Although it has several more steps than the modes discussed earlier, a dedicated source-synchronous mode makes the setup process straightforward. These steps can be viewed as a setup "pyramid" consisting of successive layers of configuration choices (Fig. 4). The steps are numbered in the order in which they are normally performed. Let's follow the process from "bottom to top."

1. Assign Edge Detectors: Every synchronous digital system requires a clock. Source-synchronous systems also use one or more strobe signals. The logic analyzer implements edge detectors to mark the passing of such events. Four edge detectors are available per module, with rising and falling edges assigned independently from one another. Linking the strobe signal to a detector completes the logic analyzer's definition of when a cycle's data is valid.
2. Bind Edge Detectors Into Clock Groups: A clock group consists of one or more of the previously defined edge detectors. In turn, the clock group defines exactly which edges are needed to complete an event.
3. Define Sample Clocks: The validity of SUT operations, such as Read or Write, are determined by Boolean conditions that encompass several signals. Setting up the sample clocks prepares the logic analyzer to sample according to these Boolean equations. Just as the clock groups are made up of edge detectors, the sample clocks consist of clock groups related by various Boolean OR and AND invocations using qualifier signals.
4. Setup Group Clocking: The group clocking setup step is the point at which all of the previous definitions—edge detectors, clock groups, and sample clocks—converge. The group clocking menu also imposes timing parameters on all of the logical conditions programmed so far.
5. Define Probe Demultiplexing: Probe demultiplexing tells the logic analyzer which groups to demultiplex so that they're consistent with the source-synchronous acquisition. The logic analyzer has default mappings for various levels of demultiplexing, which are satisfactory for source-synchronous acquisitions. Therefore, this setup step simply specifies the default map. Figure 5 shows the result of a source-synchronous acquisition. Here, the strobe latches data on its rising edge. This data is then resynchronized to the master clock, as shown in the waveform view.

To increase the data throughput in digital systems, innovative data-transfer techniques are gaining popularity. These include increasing the basic clock and data speed, sending the data differentially, reducing the signal amplitude, transferring data multiple times in one clock cycle, and sending the data in a source-synchronous format.

When capturing the digital data from the buses implementing these transfer attributes, it's necessary to use an advanced logic-analysis tool that can capture these types of buses without the need for a front end "preprocessor" to manipulate-and possibly distort the data.

A new generation of logic-analyzer modules is rising to meet this need. These tools can handle high-speed synchronous clocks and capture multiplexed bus data and source-synchronous data transfers.