Memory density has traditionally been a key technology driver that has taken center stage in the digital technology papers at past International Solid-State Circuits Conferences (ISSCCs). But this year's presentations, which took place earlier this month in San Francisco, Calif., focused more on performance issues. Improved bandwidth on memory buses and higher-speed processor buses are key developments that will deliver higher system performance.
With that said, this year's ISSCC didn't disappoint designers who wanted to hear about the latest high-density DRAMs, SRAMs, and nonvolatile memories in Sessions 24, 11, and 2. Multigigahertz CPUs also were hot subjects at this year's conference, with close to half a dozen presentations that detailed CPUs and compute blocks running at clock speeds that exceeded 1 GHz. These were detailed in Sessions 15 and 20. Additionally, high-speed bus interfaces, with data-signaling speeds of up to 6.4 Gbits/s, were the highlight of Session 4, while Session 25 covered high-speed clocking schemes.
The one memory paper at ISSCC that pushed density to the maximum described a 4-Gbit double-data-rate synchronous DRAM developed by researchers at Samsung Electronics, Kyungki, Korea (paper 24.1). Thought to be the first chip to contain over 4 billion transistors, the memory occupies a rather healthy chip area of 645 mm2, even with the use of 0.1-µm design rules.
To minimize inter-bit-line coupling noise in the large array, the memory employs a twisted open-bit-line architecture. Additionally, a gain-controlled presensing scheme and active calibration of the bit-line precharge voltage are used. Both help to improve the sense-amplifier sensitivity and sensing margins.
In a presentation in the same session, Elpida Memory Inc., Kanagawa, Japan, focused on a technology also capable of producing multigigabit DRAMs. (Elpida is a partnership company formed by Hitachi Ltd. and NEC Corp.) The researchers employed 0.13-µm design rules to develop the process that combines an open-bit-line trench-capacitor memory cell, a distributed overdriven sensing scheme that operates below 1 V, and a stacked flash-fuse structure to control the redundant memory rows and columns.
The fuse structure consists of three series flash fuses fabricated with standard CMOS transistors that don't require any additional process steps (Fig. 1). The resulting OR function can reduce the fuse failure rate by almost 10 orders of magnitude versus the traditional metal-link fuses, improving production yields. Designers verified this combination with a 256-Mbit test chip that achieved a 208-MHz cycle time in the memory array.
Details of the first 512-Mbit DRAM with a second-generation, 600-Mbit/s, double-data-rate interface (DDR2) were unveiled in a paper jointly presented by researchers from IBM Corp. and Infineon Technologies, both located in Hopewell Junction, N.Y. The improved interface allows the memory array to accept a column-address-strobe (CAS) command immediately after the row-address-strobe command (RAS) is issued. The CAS command and address are then held in an address FIFO buffer for the duration of the address latch signal.
In contrast, the first-generation DDR interface typically has a RAS-CAS delay time of about 13 ns. That requires at least four cycles of a 300-MHz clock, which reduces bus efficiency. Thanks to the elimination of the delay, the DDR2 interface can handle back-to-back RAS commands, achieving 100% bus utilization and a 600-Mbit/s data transfer rate on each data pin.
The three other DRAM papers presented in Session 24 focused on the design of embedded DRAM (eDRAM) macros. The first in that group, delivered by a joint development team from Mitsubishi Electric Corp., Hyogo, Japan, and Matsushita Electric Industrial Co. Ltd., Kyoto, Japan, targeted low power consumption. United Memories Inc., Colorado Springs, Colo., and Sony Corp., Tokyo, Japan, jointly presented the second eDRAM presentation, which took aim at high-performance graphics applications. Mitsubishi ended the session with a second eDRAM macro that the company developed to deliver a very flexible solution.