Talus Hydra anchors a full hierarchical
methodology that supports bottom-up,
block-based flows, top-down black-box
flows, and mixed flows with automated
floorplanning, partitioning, and time budgeting.
It enables early design planning
using a netlist consisting of a mix of gates,
RTL, macros, black-box models, and
GlassBox models. It affords quick feedback
on design prototypes for floorplan,
design, and timing-constraint refinement.
Ciranova plans to show its Helix tool.
It’s an automated analog layout suite that
optimizes both circuit and device layout
simultaneously, delivering design-rule-correct placement comparable
in quality to that produced by an experienced layout
designer, claims the company. Using Ciranova Helix, analog and
custom designers can explore multiple layout alternatives in minutes,
allowing them to get higher-quality designs to market in a
fraction of the time needed by conventional methods.
With Helix’s fast runtimes, designers can explore multiple
layout alternatives and even extract parasitics early in the design
process. Benchmark results include placement of a 154-transistor,
phase-locked-loop (PLL) circuit in under four minutes.
Ciranova Helix’s primary inputs are a Spice netlist and a
Process Design Kit (PDK) containing either Cadence SKILL
PCells or Ciranova PyCells, such as those in the Interoperable
PCell Library (www.iplnow.com). Helix is a native OpenAccess
tool, which integrates seamlessly into OpenAccess-compatible
environments such as Cadence’s Virtuoso, Silicon Canvas’
Laker, and Magma’s Titan, as well as DRC tools like Mentor
Graphics’ Calibre and Synopsys’ Hercules. Ciranova Helix is
available now.
GOING FOR LOW POWER
DAC is the place to be this year for low-power designers, with tutorials,
paper sessions, and several workshops delving into the how-to’s
of designing low-power SoCs. Minimizing SoC power consumption
has become a prime design goal, especially for multiprocessor
SoCs, where peak temperature limits are of high concern.
Sequence Design is planning to show its PowerArtist tool,
which focuses on power reduction at RTL in three key areas:
clocks, memory, and datapath. The tool’s analysis engines examine
the design’s RTL code, prioritize design hotspots, and deliver
power reduction in one of two ways. It can operate in automatic
mode or guide the user through manual edits within a graphical
user interface (Fig. 4).
PowerArtist can be integrated with all design flows, including
synthesis and formal verification. It’s also compatible with
OpenAccess databases through its open API. Pricing starts at
$220,000 for a one-year time-based license.
An interesting entry in the low-power design arena is Envis,
formerly known as Envision Technology. At DAC, Envis will
display its range of tools for measuring and reducing power consumption.
For the power-estimation side of the equation, Envis’
Kelvin performs automatic power-pattern generation. The tool
takes in a netlist and generates vectors to estimate power consumption
for that netlist. The estimates are realistic, correlating
well with average power.
Interfacing through an API with any of the industry-standard
simulators, the tool’s vectors can be used to generate average
power estimates as well as detailed power-pattern data. Estimates
can be made early in the development cycle, when designers are
trying to choose between IP blocks for a given function.
For power reduction, Envis offers up its Chill tool, described
as a next-generation approach to clock gating. The tool automatically
partitions the circuit into power partitions that can be
turned on or off together. It inserts activity-detection circuitry
that determines when a partition is inactive and disables clocking
to that partition.
Clock gating can be done in combinational or sequential
fashion. If manual clock gating has already been imposed on the
circuit, the tool won’t override it. Instead, the tool optimizes it.
Working together, the Kelvin and Chill tools comprise a
powerful methodology for estimating and reducing power consumption.
After synthesis, a Kelvin run on the netlist establishes
a baseline estimate before running Chill. A second Kelvin run
estimates the power savings achieved by Chill. Kelvin can be run
again after physical design for an even more accurate estimate
that includes parasitics. Both Kelvin and Chill are available now.
Chill sells for $180,000 for a one-year, time-based license, while
Kelvin sells for $50,000.
An increasing concern for power designers is the interaction
between their ICs, the packages they reside in, and the circuit
boards they’re attached to. A systemic approach can reduce
design risk and optimize system cost. To that end, Apache
Design Solutions will be at DAC with its Sentinel-PI, a chippackage-
system co-design tool for power integrity. Sentinel-PI
provides modeling, analysis, and optimization for IC, package,
and printed-circuit-board (PCB) designers.
Sentinel-PI generates Spice-accurate models of the full-chip
power-delivery network, which Apache terms Chip Power
Models (CPMs). The models contain parasitics of the nonlinear
switching and non-switching devices, as well as decoupling
capacitance, loading capacitance, power/ground coupling capacitance,
and effective RCs. This latest release of CPM adds inductive
effects for higher accuracy.
VERIFYING ABOVE RTL
To address the current gaps in functional verification, designers
are raising the abstraction level of design entry. At DAC this
year, we will learn about advances in functional verification of
these abstract SystemC/C++ models. In particular, there will be
presentations covering both simulation and formal verification
techniques, with special focus on handling concurrency.
Verification above RTL may be appealing, but designers can be
stymied by the lack of model availability. Where do models come
from? And how long do they take to create? At DAC, Carbon
Design Systems will demonstrate a speedier version of its Carbon
Model Studio, a tool for automatic generation, validation, and
implementation of hardware-accurate software models.
The upgrade of Carbon Model Studio includes a key debug
improvement that provides increased visibility into complex
design constructs. It offers full visibility into named and
unnamed generated blocks, VHDL composite types, and multidimensional
arrays, including nested arrays and composites.
In addition, Carbon Models have new API calls for accessing
design constructs.
With improved model validation,
designers can control the model-validation
generation process from inside
Carbon Model Studio through a new
component editor. The Model Validation
component’s mixed-language shadow
hierarchy matches that of the original
design for tighter integration into complex
testbenches, assertion languages,
and custom validation environments.
Carbon Model Studio, shipping now,
is available for Solaris and PC platforms
running Linux and Windows. Pricing
for the complete model-generation and
execution environment is “use-model”
dependent and starts at $20,000.