ANALOG MODELING ADVANCES
From Lynguent comes the ModLyng Event Driven Mixed- Signal Toolkit (EDMS), a collection of libraries containing building blocks that support the creation of models for analog devices using event-driven (digital) techniques. Models created using the ModLyng EDMS Toolkit simulate orders of magnitude faster than analog models of the same device, the company claims.
The ModLyng EDMS Toolkit is used with Lynguent's Mod- Lyng, an integrated modeling environment that enables users to create, manage, and support HDL-based simulation models for analog, digital, and mixed-signal domains by graphically assembling mathematical, functional, and behavioral building blocks into the model's topology.
IP reuse will be a key topic in the technical program at DAC this year; it also will be the subject of product and technology launches. Arteris, a provider of network-on-chip (NoC) interconnect technology, is showcasing a product called P-NoC that now enables the company to address all requirements for SoC interconnect including the top-level interconnect, block-level interconnect, peripheral interconnect, and interchip links.
The P-NoC interconnect product is optimized for connectivity of peripheral IP cores such as USB, infrared interfaces, control communications, audio, touchscreen, and others. The product also offers an efficient means of communicating to IP core register interfaces. Available now, P-NoC pricing starts at just over $100,000.
Many design teams are taking a holistic approach to chip, package, and board design in efforts to better control signal integrity. To that end, Sigrity is introducing next-generation technology for package model extraction with XtractIM Version 3.0, which will e available for production use in early July.
Rather than simply creating package models for further analysis, XtractIM users can quickly determine if the package design meets the performance requirements of the targeted chip. The software visually displays impedance and coupling along the length of signal nets in a way that enables package engineers to instantly pinpoint performance issues even in complex designs.
WHAT'S NEW IN IMPLEMENATIONS?
Getting to timing closure is one of the biggest obstacles to taping out an SoC design. With that in mind, Magma Design Automation's Talus 1.1 RTL-to-GDSII chip implementation system leverages Magma's unified data model to perform timing optimization concurrently during routing.
Included with the release is the Talus Flow Manager, which includes out-of-the-box reference flows for RTL-to-GDSII, multi- VDD, low-power design and high-performance design; engineers can easily tune the reference flows for specific applications. Also new to Talus is the Visual Volcano, an analysis environment and integrated information display that allows an engineer to quickly track many parameters of the design, including run times, timing, power, and area (Fig. 3).
At DAC, Pyxis Technology will demonstrate its NexusRoute- HPC, a custom design routing technology built to support the needs of today's digital and analog custom designers. The NexusRoute- HPC reduces design time from weeks to hours by providing highly automated hierarchical custom routing and an integrated “what-if” analysis capability. Pyxis will also show its NexusRoute-SOC, an SoC digital routing technology optimized for advanced technologies at 45 nm and below.
Of further interest to full-custom analog layout designers is Tanner EDA's schematic-driven router, which brings enhanced layout productivity. The router, which complements the company's integrated schematic-driven layout (SDL) tool and layout device generator (DevGen), is an automatic routing engine integrated directly into SDL. It speeds layout by automatically routing non-critical nets while allowing the designer to focus on routes that truly require expensive hand craftsmanship.
RTL SYNTHESIS SEES GAINS
Potentially one of the most interesting DAC launches comes from Oasys Design Systems, which will unveil its RealTime Designer, a physical RTL synthesis tool for designs of up to 100 million gates. The tool can take such large designs from RTL to placed gates in a single pass and in a fraction of the time taken by traditional synthesis, Oasys says. RealTime Designer's RTL placement approach limits synthesis-layout iterations.
RealTime Designer follows a “place-first” methodology that partitions the RTL into blocks, places the RTL in the context of a floorplan, and implements each block all the way to placement. Chip-level constraints are automatically propagated across the blocks, and the design is optimized for the best possible quality of results. Further, the tool automates the process of checking the design for congestion and other layout issues. At completion, RealTime Designer produces a placed design and a netlist that meets the constraints in the context of the desired floorplan.
Attempts to migrate designs to smaller process geometries below 90 nm are often plagued by unexpected process variation effects. Among the more pernicious of these are well-proximity effects, which can play havoc with MOSFET electrical characteristics. Typically, designers try to anticipate these issues and deal with them through heuristics-based guardbanding, but this can extract a toll in area. Or, they can iterate through a series of postlayout extracted netlists. In this case, the penalty is time.
Solido Design Automation will demonstrate its Solve Well Proximity application, which is intended for use with the company's Variation Designer tool. The combination deals with wellproximity effects by leveraging foundry-provided parameters that are included in the Spice model files but are not normally used due to the lack of appropriate tools at the circuit design stage.
Chip designers can use the application during the circuit design stage to proactively account for well-proximity effects. Designers can determine which devices are sensitive to proximity effects and by how much. They also can obtain the appropriate proximity parameter values and minimum well distances. These values are back-annotated into the schematic and are then used by the layout engineer, reducing the silicon area occupied by excessive guardbanding and eliminating iterative post-layout simulations.