Today's system-on-chip (SoC) designs incorporate various input-output capabilities and are multi-core systems with fast communication protocols. SoCs often incorporate various processing elements for multimedia and networking applications. The convergence of computing, communications, and multimedia data processing onto one chip pushes SoC complexity in two areas: SoC integration and software development.
No company today designs the complete SoC itself; they source the complement of IP cores from different vendors. Integrating IP from different vendors in a single SoC and making them work is a highly complex task. The IP vendors are under pressure to support all the popular interfaces and make their IP suitable for a wide range of customers. To address SoC integration issues, the industry has been moving toward standardizing the IP core interfaces to achieve high reuse. The Open Core Protocol-International Partnership (OCP-IP) is a standards forum focusing on SoC integration concerns. OCP-IP defines a high-performance, SoC bus-independent interface between IP cores. This makes the IP core independent of the architecture and design of systems in which they are used.
SoC developers not only need to achieve high performance, but the product also must be flexible and programmable. As a result, SoCs are becoming software intensive. Software content on these SoCs comprises low-level firmware, device drivers, telecom/communication stacks, operating system (OS) code, and application software, etc. Development and validation of so much software is a big challenge.
To address these software development challenges, the industry has been adopting more abstract simulation models, which can deliver enough performance and accuracy to enable software development to begin in parallel with chip development. In this phase, software developer goes through multiple build/execute/debug cycles and overall productivity depends on the simulation speed and ease of debug. The Open SystemC Initiative (OSCI) is a standards forum focusing on defining the standards for creating software models of SoC. SystemC is a standard language for modeling of SoC. OSCI TLM2.0 is a standard library for transaction-level modeling. OCP-IP has created an advanced modeling kit by extending OSCI TLM2.0 for the Open core protocol.
The OSCI and OCP-IP standards have the potential to address most of the challenges in current SoC designs. We at CircuitSutra have demonstrated the virtual platform by using the modeling standards from OCP-IP and OSCI. A demo virtual platform is available for free download from the OCP-IP website.
Using the virtual platform for embedded software development instead of using an FPGA board provides several advantages. It allows hardware design and embedded software development to proceed in parallel, hence reducing the time to market for electronics product. It also provides more powerful debug features needed to develop and verify complex software for a multicore SoC. This article discusses how to create an SoC virtual platform for embedded software development.
It is critical to choose the correct abstraction level when creating an SoC virtual platform. The abstraction level defines how much timing accuracy you will see in simulation as well as the functional accuracy of the hardware models. Which level is right for you? It depends on your purposes for using the virtual platform. These might include embedded software development, RTL verification, architectural exploration, and performance optimization. We will limit discussion to embedded software development, which requires use of the virtual platforms at very high abstraction levels. Various abstraction levels are relevant to this use case for a virtual platform. Blue blocks represent the virtual models. Green blocks represent the software that is developed and verified using these virtual models.
The Programmers’ View
A virtual platform that provides a level of abstraction known as the Programmers’ View (PV) includes the Instruction-set simulator (ISS) of the processor and the register accurate transaction-level models (TLMs) of the peripherals. Providing this virtual platform to the software team enables them to develop the hardware abstraction layer and device drivers and run these on the platform. They develop the complete software stack (middleware and application software) on top of this. Alternatively, instead of different layers, there can be a small embedded application which itself programs the registers of the peripherals and accesses the functionality of the SoC. The device driver and hardware abstraction layer is very much specific to particular hardware. It is critical to model correctly all the registers that are visible to device drivers and the functionality associated with these registers.
The embedded software that will execute on this virtual platform must comply with the tool chain used to create the target SoC. This platform is binary compatible with the real hardware. The binary that executes on this virtual platform can also execute on the real hardware as it is.
To create this virtual platform we need:
- The specification of the SoC, which is the same specification required by the team developing the hardware-dependent software layer, and
- The tool chain of the target SoC to cross-compile the embedded software.
When we speak of SystemC models for the purpose of embedded software development, the Programmers’ View is the most popular abstraction level used in the industry. Most TLM standardization work targets this abstraction level. The OSCI TLM 2.0 base protocol (LT methodology) and OCP-IP TL4 standards are suitable for creating the models of IP blocks at this abstraction level.
In the rest of this article we will focus on the Programmers’ View abstraction level.