With the ramp-up of 28-nm fabrication processes, system-on-a-chip (SoC) design teams are busily prepping chips that will cram more functionality into the same silicon real estate. But as with each process shrink that has come before it, the 28-nm process node will put increased pressure on both functionality and physical verification teams.
The greater gate density for a given silicon area is only part of the equation, and it mostly impacts functional verification. However, when it comes to physical verification at 28 nm, the number and complexity of the foundries’ design rules pose the most formidable challenge.
EDA vendors very closely track tapeouts across the industry at emerging process nodes. It’s their business to do so. According to one major vendor’s estimate, about 100 designs are in the pipeline at 28 nm, and roughly half of them have taped out.
With that measure of experience at the 28-nm node, the biggest trend that is taking shape in physical verification is the integration of rule checking with the placement and routing of the chip.
“I don’t remember us talking about physical verification nearly as much at 65 nm as we are now at 28 nm,” says Saleem Haider, senior director of marketing for physical design and design for manufacturability (DFM) at Synopsys.
Getting physical
The number of physical design rules has increased significantly since the 65-nm node. At 40 nm, foundry runsets totaled fewer than 1000 rules to be checked. At 28 nm, the number of rules has exploded to anywhere from 1500 to 1800 rules. Thus, according to some industry estimates, physical verification (Fig. 1) run times at 28 nm are almost four times longer than they were at 65 nm.
And while there are many more rules at 28 nm than there were at 65 nm, an even bigger issue is the increased complexity of the 28-nm rules. At 65 nm, design rules were predominantly two-dimensional. Manufacturing compliance in a given fabrication line was mostly a matter of ensuring that on-chip structures were far enough apart.
The same held true for routing lines. Keeping them a given distance from each other would be enough to keep crosstalk and other signal-integrity issues at bay.
But at 28 nm, that’s no longer enough. The laws of physics loom larger than ever, and it’s now reaching the point where design teams can no longer assume that logical design and physical design/verification are separable problems.
Just as logic synthesis eventually had to become more physically aware back at the 90-nm and 65-nm nodes, now placement and routing must look ahead to the next phase of the implementation process and anticipate what takes place in physical verification.
Continue on next page