As today’s system-on-chip (SoC) designs continue to grow in size and complexity, schedules for physical design are staying the same or shrinking. Design teams must deliver products quickly to market to capture as much revenue as possible. In response, many design teams are turning to hierarchical design flows to implement large designs, allowing them to divide the task into pieces that can be implemented in parallel, thereby compressing the overall development schedule.
This article will discuss various challenges to design exploration and design planning in a hierarchical flow for large SoCs. It will further delve into efficient techniques that produce fast turnaround times and make possible concurrent physical implementation, enabling predictable design convergence.
As an example of today’s ASIC design complexity, IBM’s Cu-32 ASIC product offering delivers 2.9K raw gates per square millimeter. Such advanced process nodes enable SoC design teams to integrate and implement extremely powerful and complex systems, and designers are taking advantage of these available gates. Experts are citing transistor counts of 2 to 3 billion for the latest processor designs and 800 million to more than 1 billion for today’s ASIC SoC designs.
Daily, the pressure increases on design teams to ship these mammoth designs. Applications ranging from smart phones, tablet computers, and automotive navigation systems to high-end network switching and computer servers utilize complex, high-gate-count SoC devices. Consumers’ appetite for better graphics, faster response times, and more functionality seems insatiable – last year’s “leading edge” is nothing compared to what is available today! Because the market window for many products is so short, the companies producing the silicon must leverage a short development cycle to survive.
How are they getting it done? Most design teams compress their development schedules by starting physical design in parallel with logical design. They reuse design data from previous designs, employ production-proven intellectual property (IP), and implement hierarchical design methodologies.
As stated earlier, hierarchical methodologies allow design teams to divide the chip into manageable pieces to implement in parallel, thus saving time. However, to achieve optimal throughput and time savings, they also take advantage of many opportunities to save time throughout the flow as the design progresses from planning through implementation. A number of timesaving opportunities are discussed later in this article.
Scheduling Logical and Physical Design in Parallel
Physical designers rarely receive a final netlist of a completed logical design before starting physical layout of the chip. In today’s environment, physical designers and logical designers start work at nearly the same time. Generally, design teams schedule a number of early netlist hand-offs, or netlist drops, from the logical to the physical designers before the “final” netlist is available. This enables physical design teams to start exploring various implementation strategies. By the time the final netlist arrives, the physical designers have developed a detailed implementation strategy that enables them to minimize the time to tapeout. Minimizing CPU runtime while working with early netlist drops enables physical designers to explore and assess more floorplan solutions. This is critical to finding the best floorplan to ensure minimum time to tapeout and highest quality of results when the final netlist arrives.
Practically speaking, functional and timing engineering change orders (ECOs) are often given to the physical designers after the final netlist. Ideally, these are relatively small in terms of the number of gates and nets affected; however, ECOs do require time and effort to implement, and they must be included in the physical layout before tapeout.
Design Reuse and Intellectual Property
Another technique that teams use to compress design schedule time is reuse of earlier design blocks and use of third party IP. It is very rare that a new chip featuring billions of transistors is designed completely from scratch. Generally, most of a new design’s transistors are used to form memories or functions derived from similar functions implemented in earlier designs.
This trend, coupled with the scheduling of early netlist drops, means that much of the gate-level content of a new design is available in early netlist drops.