The myriad challenges of designing a chip on its own range from functional correctness to power and signal integrity and manufacturability. Chips do not exist in isolation. Instead, they must be integrated into a system context both electrically and mechanically. Moreover, chips must be packaged and then attached to a circuit board. While chip/package/printed-circuit board (PCB) co-design does offer challenges, tools and methodologies are available to designers in pursuit of design closure.
Design Challenges Abound
There once was a time when chips, packages, and boards were designed serially and in that order. But at some point, signal-integrity issues for board designers, often resolved through an unoptimized design, began to dictate a systemic approach to the process.
With time constraints and short design cycles as endemic as they are, the task of establishing systemic synergy between a chip, package, and board is extremely challenging. Right off the bat, the design team often must decide whether some aspects of the system will be considered in detail at all, or whether they will simply carry forward assumptions from previous design cycles.
IC package technology is evolving quite rapidly, and it is too often overlooked in the broader scheme. “We see packaging technology as a very big driver, almost the same in significance as power-related issues,” says Dian Yang, senior vice president and general manager of Apache Design Solutions. The primary reason is the cost of packaging, which can get out of hand quickly with some of today’s advanced technologies.
On the other hand, those expensive packages have capabilities that you can’t get in any other way. Packages using 3D IC technologies driven by through-silicon vias (TSVs), systems-in-a-package (SIPs), and chip-on-chip technology can be differentiators that factor into the device’s market success (Fig. 1). But beware: Choose the wrong package and your device may not sell because it’s too expensive, or your package choice may even result in the device’s failure in certain use cases.
“3D packaging with TSVs drives higher integration but really complicates the off-chip network,” says John Park, methodology architect in the System Design Division of Mentor Graphics (see “Thanks To TSVs, 3D IC Packaging Gets Set To Tackle Tough Challenges” at www.electronicdesign.com).
A signal path that was once a simple wire bond to a metal lead frame now involves redistribution routing to a microbump, followed by a silicon interposer to another IC and then down to the package bumps (Fig. 2).
Getting Started
An initial challenge concerns substrate and board topologies. How many signal and ground layers should comprise the package substrate and board? Tradeoffs must be made between the number of layers and routability, as cost rises dramatically with increasing complexity. This means undertaking feasibility analysis.
Once that process is completed, system-level floorplanning considerations come into play. How do I plan wirebonding and routing? Often, systems are designed with fixed DRAM chips and a custom processor. This may necessitate yet another feasibility analysis of routability and bonding options.