In the age of convergence, analog and full-custom
design is reasserting itself as a crucial aspect of almost
all system-level designs. While analog content is growing
by leaps and bounds in most IC designs, productivity for
analog designers is not.
In the early days of analog design, layouts for discrete
devices on ICs were created by what is colloquially
referred to as "polygon pushing." Devices were put
together through juxtaposing rectangular shapes on metal layers (poly) separated by diffusion layers. Subsequent
extraction processes would essentially define the
devices. This manual process was tedious, slow, and
quite error-prone.
The construction of a single transistor could comprise
the creation of dozens of geometric shapes. If your
design dictated the need for another transistor with similar, but not quite exactly the same, physical characteristics, you'd have to start all over again. Want to create
more variants, each with ever-so-slightly different lengths
and/or widths? Again, each one would need to start from
a clean slate. As circuit complexity grew, this quickly
snowballed into a showstopper.
WHAT'S A PCELL
Fortunately, along came the brilliant concept known as parameterized cells, or PCells.
PCells aren't a new idea, going back some 20 years.
Despite the fact that they weren't necessarily invented
there, PCells were what put a young EDA company called
Cadence Design Systems on the map.
PCells eliminate the drudgery and inherent risks of
manually creating variant after variant of the same basic
device. They're really nothing more than a program written in an extension language (more on
that to come). That program is, in essence, a layer of abstraction on top of polygons. "With the
PCell, you have captured the concept of a transistor with all of the geometries that are required for that transistor," says Anthony Gadient,
Cadence's Custom IC product marketing group
director.
PCells exist on three levels: the supermaster,
the submasters, and instances (Fig. 1). Once you
have created an original PCell, that specific set
of geometries can be considered the supermaster. That supermaster resides in the design database and contains the definitions of all the parameters that apply to the PCell geometries (the basics
are length, width, and so on) and their default values, as
well as the program used to create it.
"In essence, the supermaster is an image of the program itself subjected to default parameters," says
George Janac, CEO and founder of Silicon Navigator.
From that single supermaster, a designer can create
what's known as a process design kit (PDK) for the
device. The PDK contains the program, the PCell supermaster, Spice models, schematic symbols for the device,
and design-rule checking rule decks, among other items.
When editing a layout in a tool such as Cadence's Virtuoso layout editor, designers can create versions of that
master with non-default parameter values.
These new altered versions of the supermaster are
retained in virtual memory as submasters. When designers create a new instance, and a submaster with the
same parameter values already exists in virtual memory,
the new instance references the existing submaster cell.
The software does not generate a new submaster.
This style of design is a boon to those who craft PCells
and PDKs. Early in the PCell game, Cadence took the ball
and ran with it, putting together a full-custom design
infrastructure that remained largely unchallenged for
many years.
The basis of Cadence's approach to PCells and their
construction lies in its proprietary SKILL language. SKILL
is an immensely powerful language that contains all of
the functions one would need to construct a library of
PCells and use them effectively in analog layout. Today,
some 90% of all analog design is done using PCells, and the vast majority of that is with the SKILL language and
with Cadence's Virtuoso design platform.
CLOSED CIRCUIT
For some, however, the proprietary nature of the SKILL language is a stumbling block.
Because the language is closed, tools from other EDA
vendors that might be useful in the design flow are
unable to interpret the SKILL-based PCells. So for the
most part, PCell users have been locked into the SKILL
language and the Cadence flow.
"This means that any layout developed using PCells
over the past 15 years or more means that that legacy is
locked into a prison of Cadence's proprietary technology,"
says Kevin Steptoe, vice president of marketing and business development at Pulsic Ltd.
It's not just the issue of a locked language, either.
PCells and PDKs created using SKILL and Virtuoso support only a given foundry process. "The real issue is at the
interplay between the foundry, the EDA vendor, and the
customer," says Dave Millman, vice president of marketing at Ciranova Inc.
PCell consumers want a greater range of interoperable
process coverage from their PDKs, with kits able to span
multiple foundries, processes, and EDA tool flows.
"Today, the process coverage is focused on only one EDA
vendor," says Duncan Widman, senior PDK engineer at
Applied Wave Research (AWR).
For the foundries, the ability to migrate PDKs among
processes is a huge issue. They continue to develop
new process variants for low power and low leakage current. And some of those foundries' largest customers,
the large integrated device manufacturers (IDMs), work
with multiple foundries. In-house PDK developers who
build and maintain the kits develop most of their PDKs
internally.
"PDK resources are very scarce, and good PDK developers have handcuffs on, whether they're in foundries or
at IDMs or at EDA vendors," Widman says. "You can't
solve this problem with more resources, or by covering
every node as we do it today. The industry has to come
together on an easier way to
solve it."