A new tool has arrived that fully automates the process of synthesizing highly optimized pipelines. To augment its existing Volare synthesis environment, Get2Chip Inc., San Jose, Calif., has created Pipeline Master. This tool completely automates the optimization of all critical parameters for pipelines (Fig. 1).
In the design of processing engines, pipelining is considered a crucial technique that can greatly increase the unit's throughput. Pipelines are especially useful for brute-force calculations that repeat over and over. In fact, pipelining can even be applied to nonprogrammable engines, such as a hard-coded encryption engine. Whether or not the calculation engine being pipelined is programmable, pipe-lining lets a circuit process multiple sets of data in parallel, but staggered by one or more clock cycles.
Historically, pipeline design has been a manual and time-consuming process. Working in handwritten code at the register-transfer level (RTL), designers have had to design, evaluate, and redesign while analyzing their results for each of the multiple tradeoffs required.
For example, one might design a pipeline that's perfectly optimized for the area it consumes in silicon. Adding another variable to the equation, like data rate, would necessitate starting from scratch and recoding all over again. Some designers try a "spreadsheet" form of analysis, but such analyses typically don't model all sources of timing.
Moreover, even a redesign of an existing pipeline for a different silicon process will require a fresh approach and a new cycle of hand coding. Changes in process geometries are unpredictable as to how physical effects will scale when you move your device, say, from a 0.15- to a 0.13-µm process. There has been little choice but to start over, re-evaluating all of the various tradeoffs that one must make in a pipeline design.
Pipeline Master ac-counts for all elements in what Get2Chip calls the "pipeline implementation space." Elements include the number of stages in the pipeline (which translates into the pipeline's latency), how operations are assigned to each stage, the input data rate, and the clock frequency. All of these parameters are considered by the tool concurrently as it automatically implements many different versions of the design. In the process, the tool searches for the right mix of attributes to deliver the best possible throughput.
Each version of the pipeline implemented by the tool is referred to as a "transformation." It's derived from highly accurate timing calculations using process-accurate models. The versions are produced by interweaving high-level and logic syntheses. Transformations are automatic explorations of different structures. For example, the tool might try an extra adder or memory port(s) for a given pipeline scheme to decrease design latency by one or more clock cycles.
As transformations are arrived at, the tool examines elements of its performance, such as wire delays and multiplexers, on a physical level. The results of its analyses are fed back into the engine, which makes the tradeoff decisions. Delays aren't looked at on an integer level, but rather in objective fashion. In other words, the delays are objectively quantified. So the tool continually and automatically evaluates and re-evaluates the results of various implementations, much as the designer might have done manually, but at much greater speed.