An Insightful View
Some insight into the tool's functionality can be gained by looking at its graphical user interface (Fig. 2). In this example, the upper right-hand window, labeled HDL (hardware description language), shows a Verilog source-code fragment with a FOR loop that includes one clock edge, @posedge ck. In the upper center, the Data Flow Graph window, labeled DFG, illustrates the flow of that loop after high-level synthesis. In this example, the tool implemented a multistage pipeline with banks of registers, indicated by rectangles, between the stages.
The window at the lower left, labeled FSM, provides a finite state-machine diagram of the code. State "s20" processes the conditional IF and branches to state "s19" when the condition isn't met. In the exit branch, the pipeline is flushed.
At the lower right is the Schematics window, which portrays the code's block diagram. Comparator "comp_uns1" is highlighted in yellow by dint of its selection in the HDL window. The "comp_uns_A28" component is highlighted in red because the cursor is pointing at that object.
Lastly, the Sharing window at the upper left shows the distribution of hardware resources. The function "f" is shared twice in the pipeline's two stages.
Together, these various views of the design let users visualize it in both abstracted and detailed terms. They give users an analysis basis for manual control of pipeline parameters, aiding in both initial design and subsequent debugging.
The views are all linked and cross correlated, with the HDL source-code window being the prime control window. The various views can't be edited directly, thereby preventing the creation of incorrect or infeasible designs through manipulation. Changes must be made in the source code, from which the tool will generate only feasible designs.
Behind the tool stands a rich command set that lets users capitalize on the tool's analysis capabilities. "You don't always want to give the tool 100% control," explains Carlson. The command set is a way to implement manual control of the tool's output.
In the overall Volare synthesis environment, Pipeline Master serves as a specialization of high-level synthesis that solves a particularly thorny, increasingly important problem. The Volare environment automatically recognizes where Pipeline Master can and should be used, and invokes it automatically. In applications that range from microprocessor design to signal processing, telecommunications circuits, encryption, speech recognition, and graphics, the tool takes on pipeline synthesis one pipeline at a time. The tool's output is fed in through Volare's RTL and logic synthesis engines, and reoptimized in the context of the overall design.
Price & Availability
Pipeline Master is sold separately or as an option to the Volare design environment. Separate pricing for Pipeline Master is $25,000, while Volare costs $100,000. Pipeline Master began full volume shipment on December 3. Hardware platforms include Sun and HP workstations, plus PC (under Linux).
Get2Chip Inc., 2107 North First St., Suite 350, San Jose, CA 95131; (408) 501-9600; fax (408) 501-9610; www.get2chip.com.