Going one step further, the ASIC’s "structure" lets EDA vendors customize their tools to automatically consider issues like vendor-specific design-rule checking and power-grid analysis prior to customer handoff. Not only is the design flow streamlined, but it also leads to lower risk for the designer by having handoff considerations handled in the tool, not by the ASIC vendor.
The technical features of a structured ASIC provide additional engineering and schedule benefits as compared to a cell-based solution. Figure 3 summarizes the design flows for the two approaches. Significant differences exist between these two design flows that affect the required engineering support, cost, and schedule to be evaluated by OEM system designers when selecting a design approach.
DFT Helps Save
Added savings in schedule, engineering support, and cost can be realized during the DFT phase of the design flow. Structured ASIC products are typically developed with an architecture that encompasses predesigned DFT functions. For example, the XPressArray product includes a DFT scan multiplexer in each individual macro with a flip-flop. This significantly reduces the engineering effort required to manage DFT timing issues in the timing-closure loop. With a cell-based ASIC, the flip-flops and DFT functions are separate cells. Because the physical routing interconnect between these cells varies from flip-flop to flip-flop, cell-based ASICs typically have a greater number of DFT timing issues. This ultimately requires more engineering effort to resolve.
Designers of structured ASICs also realize significant savings in engineering time compared to a cell-based ASIC. This is accomplished by eliminating the floorplanning phase of the design process.
Structured architectures are predesigned with an inherent floorplan. For example, the I/O, memories, and timing generators in the XPressArray product are predesigned with a fixed placement in the architecture. Although cell-based ASICs need more flexibility in the placement of these functions, they also require many iterations of the physical design placement to resolve timing and packaging issues caused by variations in the physical design. This requires a great deal of engineering effort and schedule.
Compared to cell-based ASICs, OEM system designers also realize significant cost and schedule savings during the prototype fabrication process. For example, the typical turnaround time from design sign-off to prototypes is one to two weeks. This same effort is typically 8 to 10 weeks for a cell-based ASIC. Cost savings is achieved because the tooling cost of the array’s predesigned portion is shared across many designs, while custom tooling is required for each masking step of a cell-based ASIC. For example, the design’s specific tooling cost for a 0.18-micron XPressArray design can be as low as $30K, while the typical tooling cost for a 0.18-micron cell-based ASIC is $300K.
Designers clearly have many advantages to consider when going to a structured ASIC: NRE cost is just a fraction of a cell-based ASIC; piece-part cost is substantially less than an FPGA; and migration from FPGA-based prototypes is streamlined. Moreover, customized synthesis technology brings another advantage—performance. This may be surprising, given that the architecture inherently isn’t as high performance as a cell-based approach. But by customizing the synthesis process, much of this performance can be regained by the design tools.
Custom synthesis uses direct information about the devices to pick the best possible cells for a function, and can specifically tune datapath and arithmetic operator generation to that unique fabric. With the fixed ratio of flip-flops, inverters, multiplexers, and NANDs, custom synthesis will ensure that ratios between the various types of primitives are met, thereby improving both timing and area. Structured ASICs have opened many possibilities to improve upon current synthesis flows and techniques.