Record Number Of Exhibitors
Of course, a technical conference alone doesn't make a trade show. This year's DAC will have a record number of exhibitors, many of whom will premiere new products for the first time anywhere. When you need a change of pace, head out onto the show floor and into the demo suites. There you will be able to glimpse numerous new EDA products, including the following:
Signal-integrity analysis: With process geometries shrinking and clock frequencies rising, it's critical for SoC designers to address signal-integrity problems so they meet timing closure. To meet this crucial need, Synopsys will show its new PrimeTime Signal Integrity (PrimeTime-SI) product, intended to detect and resolve crosstalk on 0.18-µm and below SoC designs (Fig. 1). It includes an integrated delay calculation engine that accurately models and computes the signal timing deviation (speedup or slowdown of nets) due to crosstalk. Customer evaluations show that PrimeTime-SI's timing estimates correlated to between 5% and 10% of Spice on most nets.
ASIC synthesis: With most ASIC designs running between 500,000 and 1 million gates (according to research by Collett International), productivity in ASIC synthesis has become a major hurdle in the time-to-market race. Synplicity Inc. is unveiling its Synplify ASIC tool, billed as the industry's first timing-driven ASIC synthesis product optimized to improve productivity for most ASIC designers. The software is said to offer runtimes of up to 10 times faster than traditional synthesis products. It also brings a top-down design methodology to the table. This methodology enables designers to perform timing-driven synthesis on designs of up to 2 million gates in a single operation, supporting matching hierarchy and constraints in synthesis and place-and-route steps.
Speed begets productivity, and the Synplify ASIC software uses Synplicity's Behavior Extracting Synthesis Technology algorithms and Synthesis Constraint Optimization Environment to greatly accelerate the synthesis of ASICs. Productivity is enhanced too by the elimination of the need for complex scripts and commands. The company believes that users can become proficient in a single day.
SoC routing: Routing is one of the most crucial parts of physical design. Now that more SoCs are being implemented in 0.13-µm processes, existing physical design tools are in danger of running out of steam. Plato Design Systems, a recent startup, hopes to have the answer in its NanoRoute tool.
The scalable router is said to be based on the industry's first graph-based routing technology. It's claimed to deliver more than a tenfold speed increase compared to the fastest grid-based routers. At the same time, NanoRoute offers the flexibility of gridless routers. Designers can use a single router for both block-level and full-chip-level routing. Additionally, the tool is capable of parallel routing on multi-CPU workstations for runtime speed and capacity increases that are commensurate with the number of CPUs.
Wireless SoC design: With the wireless market booming, designers seek tools that allow them to focus on their core competencies rather than on the issues related to the design flow itself. At DAC, Cadence Design Systems will demonstrate a wireless SoC design flow that incorporates RF and DSP design, platform-based design, optimization and verification, and datapath synthesis. The flow consists of a number of point tools, including Signal Processing Worksystem (SPW), Spectre RF simulator, Virtual Component Co-Design (VCC), NC-Sim mixed-language event simulator, Ambit BuildGates synthesis tool, and Quickturn verification systems (Fig. 2).
Front-end SoC design flow: In some approaches to a front-end SoC design, the tools force designers to learn physical layout. Tera Systems' TeraForm 2001.1 RTL design planning tool enables designers to focus on register-transfer-level (RTL) design creation and optimization. Resultant designs can then be handed off to a physical implementation team with a better starting point for existing gate-level synthesis and layout tools.
The 2001.1 release of TeraForm offers two new package alternatives: TeraForm-VP for RTL design exploration and TeraForm-EX for RTL handoff to logic synthesis and physical layout.
Analog SoC design tools: For designers looking to incorporate analog-to-digital converters (ADCs) within SoCs, two products from Fluence Technology will help. One, ADCBIST, enables users to quickly implement a built-in self-test (BIST) methodology for at-speed testing of ADCs in complex SoCs. Another, ADCBIST Developer, allows users to determine BIST requirements and simulate performance of ADCs before first silicon.
Verification: Forte Design Systems will weigh in at DAC with a new version of its QuickBench tool. The test-bench automation software offers a flexible environment that supports multiple languages, including C/C++ and RAVE, which is Forte's proprietary verification productivity language. The company will show a new version of its Cynthesizer C++ synthesis tool as well.
Also on the verification front, TransEDA plans to show a new system-level verification solution for ASIC, FPGA, and SoC designers. The product will integrate verification IP and system-level test-bench automation for verification of custom designs in a realistic environment.
Web-based design environments: A trend that has emerged over the last few years, coincident with the rise of the Internet, has been EDA tools and solutions that foster online collaboration between geographically dispersed design-team members. At DAC, Innoveda Inc. will roll out its DxDesigner, a Web-based application that forms the gateway linking computer-aided engineering and team-based design collaboration. The tool combines four key process technologies: a component information system; design entry and sharing; simulation and planning; and enterprise connectivity. It enables team members to coordinate their efforts and use a centralized, corporate-approved parts library. It also relies on hierarchical design techniques to enable reuse of common or standard subsystems in future designs.
With both its top-notch technical program and its leading-edge exhibits, the 38th annual Design Automation Conference has more than earned its reputation as one of the premier gatherings for the electronics OEM industry.
Record Number Of Exhibitors
Of course, a technical conference alone doesn't make a trade show. This year's DAC will have a record number of exhibitors, many of whom will premiere new products for the first time anywhere. When you need a change of pace, head out onto the show floor and into the demo suites. There you will be able to glimpse numerous new EDA products, including the following:
Signal-integrity analysis: With process geometries shrinking and clock frequencies rising, it's critical for SoC designers to address signal-integrity problems so they meet timing closure. To meet this crucial need, Synopsys will show its new PrimeTime Signal Integrity (PrimeTime-SI) product, intended to detect and resolve crosstalk on 0.18-µm and below SoC designs (Fig. 1). It includes an integrated delay calculation engine that accurately models and computes the signal timing deviation (speedup or slowdown of nets) due to crosstalk. Customer evaluations show that PrimeTime-SI's timing estimates correlated to between 5% and 10% of Spice on most nets.
ASIC synthesis: With most ASIC designs running between 500,000 and 1 million gates (according to research by Collett International), productivity in ASIC synthesis has become a major hurdle in the time-to-market race. Synplicity Inc. is unveiling its Synplify ASIC tool, billed as the industry's first timing-driven ASIC synthesis product optimized to improve productivity for most ASIC designers. The software is said to offer runtimes of up to 10 times faster than traditional synthesis products. It also brings a top-down design methodology to the table. This methodology enables designers to perform timing-driven synthesis on designs of up to 2 million gates in a single operation, supporting matching hierarchy and constraints in synthesis and place-and-route steps.
Speed begets productivity, and the Synplify ASIC software uses Synplicity's Behavior Extracting Synthesis Technology algorithms and Synthesis Constraint Optimization Environment to greatly accelerate the synthesis of ASICs. Productivity is enhanced too by the elimination of the need for complex scripts and commands. The company believes that users can become proficient in a single day.
SoC routing: Routing is one of the most crucial parts of physical design. Now that more SoCs are being implemented in 0.13-µm processes, existing physical design tools are in danger of running out of steam. Plato Design Systems, a recent startup, hopes to have the answer in its NanoRoute tool.
The scalable router is said to be based on the industry's first graph-based routing technology. It's claimed to deliver more than a tenfold speed increase compared to the fastest grid-based routers. At the same time, NanoRoute offers the flexibility of gridless routers. Designers can use a single router for both block-level and full-chip-level routing. Additionally, the tool is capable of parallel routing on multi-CPU workstations for runtime speed and capacity increases that are commensurate with the number of CPUs.
Wireless SoC design: With the wireless market booming, designers seek tools that allow them to focus on their core competencies rather than on the issues related to the design flow itself. At DAC, Cadence Design Systems will demonstrate a wireless SoC design flow that incorporates RF and DSP design, platform-based design, optimization and verification, and datapath synthesis. The flow consists of a number of point tools, including Signal Processing Worksystem (SPW), Spectre RF simulator, Virtual Component Co-Design (VCC), NC-Sim mixed-language event simulator, Ambit BuildGates synthesis tool, and Quickturn verification systems (Fig. 2).
Front-end SoC design flow: In some approaches to a front-end SoC design, the tools force designers to learn physical layout. Tera Systems' TeraForm 2001.1 RTL design planning tool enables designers to focus on register-transfer-level (RTL) design creation and optimization. Resultant designs can then be handed off to a physical implementation team with a better starting point for existing gate-level synthesis and layout tools.
The 2001.1 release of TeraForm offers two new package alternatives: TeraForm-VP for RTL design exploration and TeraForm-EX for RTL handoff to logic synthesis and physical layout.
Analog SoC design tools: For designers looking to incorporate analog-to-digital converters (ADCs) within SoCs, two products from Fluence Technology will help. One, ADCBIST, enables users to quickly implement a built-in self-test (BIST) methodology for at-speed testing of ADCs in complex SoCs. Another, ADCBIST Developer, allows users to determine BIST requirements and simulate performance of ADCs before first silicon.
Verification: Forte Design Systems will weigh in at DAC with a new version of its QuickBench tool. The test-bench automation software offers a flexible environment that supports multiple languages, including C/C++ and RAVE, which is Forte's proprietary verification productivity language. The company will show a new version of its Cynthesizer C++ synthesis tool as well.
Also on the verification front, TransEDA plans to show a new system-level verification solution for ASIC, FPGA, and SoC designers. The product will integrate verification IP and system-level test-bench automation for verification of custom designs in a realistic environment.
Web-based design environments: A trend that has emerged over the last few years, coincident with the rise of the Internet, has been EDA tools and solutions that foster online collaboration between geographically dispersed design-team members. At DAC, Innoveda Inc. will roll out its DxDesigner, a Web-based application that forms the gateway linking computer-aided engineering and team-based design collaboration. The tool combines four key process technologies: a component information system; design entry and sharing; simulation and planning; and enterprise connectivity. It enables team members to coordinate their efforts and use a centralized, corporate-approved parts library. It also relies on hierarchical design techniques to enable reuse of common or standard subsystems in future designs.
With both its top-notch technical program and its leading-edge exhibits, the 38th annual Design Automation Conference has more than earned its reputation as one of the premier gatherings for the electronics OEM industry.