DAC Gets Wild And Crazy

Like many niches in the electronics industry, EDA has a bit of a split personality. By day, it's typically all about algorithms, languages, standards, and myriad other aspects of putting together cohesive design and verification flows. But EDA also has its wild side, which is most visibly displayed at the annual Design Automation Conference (DAC).

This year's 44th DAC (San Diego, June 4-8) will be no different. As night falls and the show floor goes dark, ties are loosened, hair is let down, the music gets loud, and the parties crank up to a fever pitch. Mixing some of that "party-animal" attitude with its relentless hunt for the Next Big Thing, DAC's technical program includes a Tuesday special session titled "Wild And Crazy Ideas" (WACI). The session will tackle some thought-provoking notions that are less incremental and more revolutionary.

The conference as a whole explores some emerging trends in EDA that show promise in terms of growth. One that stands out is automotive electronics (see "DAC Goes On The Road,").

As always, DAC attendees will be able to roam the show floor with its booths and integrated demo suites. There, they can peruse the vendors' offerings in any and all areas related to EDA.

ESL: FROM THE TOP
Continually evolving electronic system-level (ESL) flows help to facilitate transaction-level modeling (TLM) work for early architectural exploration. At DAC, Bluespec and EVE will team to show an integrated platform for ESL verification, modeling, and architectural design.

The pairing of EVE's ZeBu hardware-assisted verification platforms and Bluespec's ESL synthesis tools results in a single development environment for models, transactors, implementations, and synthesizable verification testbenches, as well as a rich foundation library of intellectual property (IP). With the speed of EVE's FPGA-based environment, Bluespec's synthesizable transactors and models enable a seamless, heterogeneous mix of models, implementations, a verification testbench, and software models connected through transactors (Fig. 1).

CoWare plans to show the latest release of its platform-driven ESL environment for hardware designers, plus the integration of that platform with its Virtual Platform Product Family for software developers.

The latest release of the Virtual Platform Product Family addresses challenges associated with software development for multicore platform-based design. New features include automated packaging and licensing of a binary executable virtual hardware platform, which can be distributed across the enterprise and to partners and customers. The CoWare Virtual Platform Product Family starts at $10,000 U.S. list, based on the configuration.

Low-power design is on almost everyone's minds these days, even in the rarefied ESL domain. ChipVision Design Systems will exhibit ESL technology that lets RTL designers work interactively with system-level descriptions to generate power-optimized RTL code. It creates implementation tradeoff options for RTL designers and immediately and accurately implements their visualized choices (Fig. 2).

The company claims that using this technology at the system level to analyze power results in 75% pre-RTL energy savings; shortens time-to-results by a factor of 60; and creates code that's nine times more compact.

Yet another offering at DAC aims at visually oriented architectural development. Version 2.1 of CoFluent Design's CoFluent Studio enables performance analysis of complex hardware/software systems through a unique mapping technology. With it, explicit and dynamic specifications can be decided on early in the process.

FRONT-END DESIGN
RTL has become a more or less commoditized area. Yet there's always room for incremental improvements in RTL. Chip Estimate's InCyte chip-planning system now predicts chip performance along with accurate estimation of die area, power, and packaged chip cost. This arms users with feedback on the feasibility of achieving performance targets, along with die area, power, and packaged chip cost. InCyte starts at $35,000/per year.

In addition, more than 20 IP suppliers will present the latest news about IP in the Chip Estimate booth. Visitors to the booth can also put together a chip plan in less than 15 minutes and leave DAC with a spec, a plan, and a report.

IC design is truly a global affair, with collaborators, vendors, and support coming from all corners of the planet. IC Manage will show its GDP (Global Design Platform), a data-management system that offers design assembly, derivative management, and real-time worldwide delivery.