THE VERIFICATION FRONT
A longstanding concern for
many designers is the absence of objective quality assurance
in systems-on-a-chip (SoCs) and blocks of intellectual property (IP). Certess Inc. will unveil the Certitude product,
which it terms a "functional qualification" tool. Certess'
patented mutation-analysis technology objectively analyzes,
measures, and enables the improvement of functional-verification environments for complex
designs. Pricing starts at $100,000 for a one-year
time-based license.
OneSpin Solutions GmbH will show an
enhancement of its flagship OneSpin 360 Module
Verifier (360 MV) software. The tool simultaneously verifies multiple configurations that can be
generated from a configurable IP block, significantly reducing the time, effort, and cost incurred
by multiple, individual verifications. The
enhanced 360 MV supports the verification of IP
with configurable functionality ().
On the broader verification front, Cadence
Design Systems will arrive at DAC with an
upgrade to its Virtuoso multimode simulator
(MMSIM). Version 6.2 includes improvements to the common infrastructure supporting multimode functionality. In this way, Cadence hopes to address the risks and cost
inherent in full-system integration.
A common, fully integrated database of netlists and models
lets MMSIM v6.2 simulate analog, RF, memory, and mixed-signal designs and design blocks ().
Since coming onto the scene, Carbon Design Systems has
focused primarily on speeding up generated software models. At DAC, it will demonstrate added resources that accelerate system performance in addition to model performance.
Through what's termed Carbon On-Demand technology, Carbon's tools will begin leveraging the fact that most hardware
models, especially in SoCs, are dormant most of the time. Carbon will also unveil its Model Distribution Program, which
enables Carbon users to distribute the same Carbon models
they're using internally to their external and internal customers.
PHYSICAL DESIGN
Planning and optimization of I/Os
across the multiple domains of ICs, packages, and printed-circuit boards (PCBs) is a growing timesink, not to mention a
source of increasing cost. At DAC, Sigrity will display OrbitIO Planner, a tool that provides a full physical view of all
interconnect domains comprising a system, as well as the
ability to explore and optimize the I/O interfaces across these
domains. With shipping ensuing in the third quarter of 2007,
pricing starts at $58,000 for a one-year license.
Apache Design Systems will unveil its Sentinel power- and
noise-analysis tools targeted at the optimization and signoff
of package and board designs. Sentinel-CPM is a chip-system
power-integrity tool that produces a full-chip model of the IC's
power-delivery network, containing information such as on-die
decoupling capacitance and switching current profile. Sentinel-CTM is a chip-system thermal-integrity solution that provides a 3D power model that generates and ultimately provides the power density for each of the chip's surfaces to
package and system thermal simulation.
Ponte integrated its YA System, a model-based technology
that provides automated design-for-manufacturing (DFM)
analysis and optimizes a design prior to tapeout, with Blaze's
Halo lithography simulator and Cadence's Virtuoso Layout
Editor. The end result is that IP and custom layout designers
can view and correct DFM issues during design. By using the
IP checker flow to correct potential issues, designers can both
eliminate yield-limiting issues and make their IP more robust
to process variability.
SoftJin will demonstrate version 3.0 of Nirmaan, a development toolkit that can be used to build post-layout and
DFM applications. The company claims a tenfold improvement in performance over previous releases. Annual licenses
start at $100,000. Version 3.0 will be available in June.
SoftJin will also introduce NXCompare, a multiformat
layout and/or mask comparator tool that provides fast, accurate, customizable, and independent verification of post-layout operations common in DFM and fracturing. Annual
licenses start at $25,000, with shipping slated for June 2007.
Claimed as the world's fastest layout viewer, Micro Magic's MAX-View will be on display at DAC. The viewer has
been shown to load and display a chip design with a trillion
transistors, with instantaneous redisplay at any zoom level.
With the viewer's interface to Mentor Graphics' Calibre,
users also can check for DRC errors. Nominally licensed for
$8000/year, MAX-View is available with license fees waived
until mid-June 2008.
Berkeley Design Automation will arrive at DAC with its
Analog FastSPICE, RF FastSPICE, and PLL noise-analyzer
tools. The company claims the tools deliver full Spice accuracy while running five to 10 times faster than any other tools
for analog and RF design verification. Berkeley's Precision
Circuit Analysis technology combines the accuracy, performance, and robustness needed to thoroughly verify gigahertz-speed designs in nanometer-scale silicon.
Sandwork Design will demonstrate updates to various
tools in its Analysis, Verification And Debugging (AVAD)
suite. SpiceCheck, a netlist-driven programmable design
checker, now supports 64-bit operating systems as well as the
Mentor ELDO and Cadence Spectre netlist formats.
Hierarchical 3D resistance and capacitance extraction was
added to Tanner EDA's L-Edit chip-layout suite for analog/
mixed-signal design. The new tool, HiPer-PX, accurately models parasitics occurring across metal layers as well as
between the metal layers and the chip substrate ().
HiPer-PX starts at $21,495 per seat and will be available
in the fourth quarter of 2007. Existing L-Edit users can add
this capability for $15,995.