THE VERIFICATION FRONT
DAC is always a premier venue for introducing new verification tools and methodologies.
For example, EVE will display the latest additions to its ZeBu line of hardware-assisted
verification platforms.
ZeBu-UF4, an ultra-fast platform, includes four Xilinx Virtex-4 LX200 FPGAs that accommodate designs of up to 6 million ASIC logic gates. Based on a PCI card with a mother-daughter scheme, the unit features an extensive low-voltage differential swing interconnect array implemented on a 68-layer pc board.
Depending on the design structure, when performing in-circuit emulation or executing synthesizable testbenches, ZeBu-UF4 can achieve maximum speeds of 20 to 40 MHz. In co-emulation at the transaction level, it can hit 20 MHz. ZeBu-UF4 is available now, starting at $60,000.
Also new from EVE is an RTL front end that extends the ZeBu Compiler from a
gate-level netlist to an RTL design description and includes FPGA-synthesis
capabilities (Fig. 4). The front end maps
an RTL design into an array of FPGAs, such as those in the ZeBu-UF4, and automatically
handles all required tasks like RTL parsing, synthesis, and partitioning. It
supports parallel and incremental synthesis and place and route. It also enables
RTL debugging by preserving RTL names in the design database. The RTL front
end for the ZeBu Compiler is available now for $10,000.
Also new on the hardware-assisted verification front is the Iridium Edition of ProDesign's CHIPit platform. It supports up to 2580 free user I/Os on eight different extension-board sites. With those I/Os, users can connect to standard ProDesign extension boards such as external memories, Ethernet inter-faces, PCI Express interfaces, or customer-specific extension boards.
The CHIPit Iridium Edition handles up to six Virtex-4 FPGAs with a flexible and programmable inter-connect topology. It handles designs with up to 6 million ASIC gates. The system will be available in September. Contact ProDesign directly for pricing.
Advanced debug capabilities continue to be added to Novas Software's Verdi automated debug system. At DAC, Novas will show SystemVerilog assertion and transaction debug capabilities.
Startup ArchPro Design Automation will be at DAC with its MVSIM, a multivoltage RTL simulator that lets users examine the effects of any voltage variation at RTL to verify multivoltage functionality, connectivity, and sequencing. The tool has been upgraded to support variable delays and power/energy analysis.
With these capabilities, designers gain accuracy by analyzing gate-level simulation with realistic delays. This permits the detection of any dynamic timing failures due to voltage variations. The tool is available now. Contact ArchPro directly for pricing information.
BRINGING UP THE REAR
Joe Costello's vision for the EDA industry will take true innovation in the
back end of the design cycle to be realized. Much of the activity at DAC will
center on design-for-manufacturability (DFM) tools as the industry continues
to search for the DFM approach that will stick in the long run. Other announcements
will be in physical design itself, be it in placement and routing or in design
closure.
On the DFM side, silicon complexity at 65 nm and below is forcing IC designers and mask makers to look to new post-layout tools such as design-rule checkers and reticle-enhancement technology that are customized for their specific design, process, and other proprietary requirements.
To this end, SoftJin Technologies' Nirmaan is a post-layout tool development
kit that enables the creation of customized post-layout tools (Fig.
5). The alternative, which is trying to force-fit standard tools into custom
applications, has often proved unworkable. At DAC, SoftJin will demonstrate
an enhanced version of the Nirmaan toolkit with specific post-layout applications
built using the toolkit.
Startup firm Nanno Solutions will debut at DAC this year. The company's tools
use a fab's actual process-variation data and transforms it into realistic data
that designers can use to improve parametric yield. These tools can be used
in the front end as well as the back end of the design cycle.
One of the tools, Nanno-WiN, is a statistics-based worst-case interconnect model generator for RC delays and crosstalk. Nanno Solutions claims the tool, based on Monte Carlo simulation and probability calculations, improves worst-case corners for RC delays and crosstalk by 70% or more compared to current worst-case models based on skew. The tool costs $150,000 per year.
Shape-based physical design is at the heart of Pulsic's Unity integrated design environment. The platform's key benefit is that the design resides in one consistent database, which reduces the cost of managing tool interfaces. The Unity environment includes floorplanning, placement, routing, editing, signal-integrity analysis, and timing closure.
The first of the Unity tools to see release, the UniPlan floorplanner, features
automatic block placement of both soft and hard macros. The hierarchical floorplanner
is specifically focused on mixed-signal designs. Future additions to the lineup
will include placement, routing, and layout-editing offerings.
While at DAC, check in on startup Athena Design Systems for a demo of its first product: a concurrent, multi-constraint IC optimization system. The company says the tool can intelligently, and incrementally, perform an analysis-optimization-repair loop on the fly using actual interconnects.
The dream of bigger, faster multimedia/gaming SoCs that work in first silicon will be unrealizable without an infrastructure at the foundries. To that end, TSMC will be at DAC to talk up its 65-nm DFM Compliance Design Support Ecosystem. TSMC has come up with a manufacturing-based unified data format to channel DFM capabilities through selected EDA tools directly to designers' workstations.
The unified format aligns DFM tools such as lithography process checking (LPC),
chemical/mechanical polishing (CMP) analysis, and critical-area analysis (CAA)
to TSMC's manufacturing-data format. This enables designers to use the same
DFM data file no matter which vendors' tools they're using. It also enables
simplified use, management, and updates to DFM analyses using these tools.