PRACTICAL VS. ADVANCED
The DFM approach taken by Synopsys splits the art into two realms: one is practical DFM that’s handled natively in place and route; the other involves advanced techniques that are expected to become critical at the 32-nm node. The former includes items such as timing, power, and critical area; via elimination and duplication; wire widening and shielding; metal fill; lithography hotspot avoidance; design-rule checking (DRC); and soft rules. The latter features items such as lithography checking, CMP simulation, and handling of stress between devices on the silicon itself.
“As for the advanced techniques, we are in the mode of monitoring these things to watch how the need for them develops,” says Haider. “They are all still in early phases of development.”
For now, Synopsys’ DFM approach is best exemplified in the recently announced IC Validator tool for physical verification. Centering on the practical DFM issues outlined above, IC Validator directly addresses the trend toward physical verification during the design process.
Rather than an iterative, implement-then-verify-then-implement- again approach, IC Validator is an attempt to bring physical design and verification together, enabling designers to build functional blocks and verify them immediately. “In this fashion, physical verification is done by the physical design team,” says Haider. “There are no handoffs and no iterations required.”
IC Validator derives much of its power and scalability from a new analysis engine that supports multicore processing. “It enables us to divide the chip into chunks amongst multiple CPUs,” says Haider. “It also lets us divide up the design-rule deck.” The result of parceling out the design and/or rule deck to multiple CPUs is near-linear scalability (Fig. 3).
To facilitate signoff-quality rule checking, Synopsys’ hybrid processing engine operates on polygons as well a sedges. “Most advanced rules at 32 nm are captured in terms of edges,” says Haider. “With simple rules, we can capture them as polygon rules and process those very fast.”
To speed the process of physical verification, Synopsys implemented the application-specific Programmable eXtendible Language (PXL), which foundries use to create rule runsets. “PXL makes the task of capturing rules more efficient and the processing of them faster,” says Haider. Use of the language can result in runsets that are two to 10 times smaller than when utilizing TCL scripts.
IC Validator, which is tightly integrated with Synopsys’ IC Compiler design environment, is available as a pushbutton flow from inside IC Compiler. Thus, it performs signoff-qualified, in-design DRC as incrementally as the designer wishes. It also automatically detects and corrects violations. In addition, the tool performs pushbutton metal fill faster and with greater density than if it’s done within place and route or in the signoff tool, says Haider.
BRINGING DFM TO THE COCKPIT
Primarily through acquisitions, Cadence has put together a full suite of DFM products to complement its implementation platform. Its 2007 acquisition of Clear Shape Technologies enabled lithography analysis to be built into the implementation flow in the form of two tools.
The first, called the Cadence Litho Physical Analyzer, marks the rebranding of Clear Shape Technology’s InShape product. The tool takes stock of the physical geometries in the design and calculates the contours for this geome try when actually printed on silicon. Those contours drive the optimization engine.
The second tool, dubbed the Cadence Litho Electrical Analyzer, covers the electrical side of the analysis coin. It also extracts contours for the printed geometries and feeds them into timing and power analysis engines
For CMP analysis, Cadence acquired Praesagus and its CMP Predictor. There are two primary use models for what is now known as the Cadence CMP Predictor: prediction of copper “hills” and “valleys,” and finding hotspots. The tool’s results drive intelligent metal fill, which chooses the optimum shape and amount of metal for a given area. What often passes for an alternative is a “metal-everywhere” approach, which carries a significant downside in the form of increased coupling capacitance.
According to Cadence’s Dave Desharnais, CMP and lithography analysis being part of the design flow has become even more important. At its recent technology symposium, TSMC declared both items as a mandatory check on the design side before design data is sent to the foundry.
“That means the design guys can’t call it a foundry problem anymore,” says Desharnais. “This opens up huge opportunities for us,” he says, and presumably for all of the RTL-to-GDSII vendors. It’s also an opportunity for the design community to take responsibility for DFM.