According to recent industry data, analog/mixed-signal and RF content occupies some 5% to 10% of the area of an increasing number of systems-on-a-chip and systems-in-a-package. However, that percentage alone can chew up 50% of the design effort and trigger 50% of the re-spins. To address the need for productivity and silicon accuracy, Cadence has rolled out new capabilities under its Virtuoso custom design platform.
Analog/mixed-signal and RF designers face core challenges that are dictated by the task at hand. These challenges include parasitic extraction and its accuracy, verification of multiple design domains, the interface between the IC and its host system, and the need for smooth interaction between design teams with very different specialties.
By basing its new approach to analog/mixed-signal and RF design around Virtuoso, Cadence is creating a "meet-in-the-middle" technique that leverages top-down speed as well as bottom-up accuracy. Two new flows, based on 802.11b WLAN IP, focus on front-to-back RF and analog/mixed-signal design while bridging the gap between IC design and system design.
Designers using Virtuoso AMS Designer can work with system design teams while leveraging the wireless standards libraries available for CoWare's SPW system-level design environment. Moving designs from IC to system level is now more efficient thanks to tight integration with the MathWorks' Matlab/Simulink. Also included in the flows are Agilent's RFDE, Momentum, and Ptolemy RF design and test technologies, plus Helic's VeloceRF inductor design tool.
Customer workshops are offered to bring designers up to speed in the new flows, as are downloadable design kits. A full suite of Virtuoso tools for the RFIC flow starts at $285,000 for a time-based license.
Cadence Design Systems
www.cadence.com/community/virtuoso