When it comes to tools, every craftsman has his or her favorites. Cabinetmakers might single out their wood planes or stonecutters their chisels. And certain tools are essential to craftsmen—they'd be lost without them. In these times of multimillion-gate ASICs, circuit designers must have EDA tools to reach tapeout. They, too, have their favorites—tools that can be relied on to solve particularly thorny problems. Designers will often complain about their design tools, but they have got plenty of good things to say as well.
For most designers and design consultants, certain tools have turned into trusted allies. Some of them, such as design planners, have emerged as consequences of the times. If you're faced with physical implementation of millions of gates that make up dozens of intellectual-property (IP) blocks, a design methodology that encompasses floorplanning, silicon virtual prototyping, or physical synthesis has become mandatory.
For other designers, the latest generation of physical implementation tools has proved itself as a more sensible way of approaching the back-end flow. Interviews with personnel at foundries, ASIC manufacturers, and design consultants have turned up a broad spectrum of opinion as to what makes a tool or methodology a "favorite." Similarly, an informal online survey elicited feedback from a range of designers on everything from Spice to system-level design tools (see "Designers Sound Off Online," p. 56).
"My favorite tools save me time rather than cost me time," says Eric Decker, an independent design consultant in Mountain View, Calif. Generally, designers should look for tools that save them time. "There are certain tools you have to run to get a design that works, but those don't necessarily save you time."
"Every tool has its sweetspot, and so I don't say that there are bad or low-quality tools," says Hideki Yamada, EDA chief technologist with the System LSI Group at Toshiba America Electronic Components Inc. As do other large ASIC and system-on-a-chip design houses, Toshiba continually evaluates EDA tools to determine whether or not they're a good fit for its design methodologies. If Toshiba's EDA group finds that a particular tool's strength matches a need in the company's flow, it'll recommend it. Otherwise, it seeks alternatives.
FRONT-END FAVORITES
The front end, or functional design portion, of the design process has seen much pressure in recent years to "clean up its act." In other words, it must pass better RTL code through synthesis and on to the back end, or physical implementation. This is approached in a number of ways, and designers cited several among their favorite tools.
"I like tools that prequalify a design before I run any simulations," says Decker. One example, and one that offers fast runtimes, is tried-and-true RTL linting. Linters examine RTL coding for proper style and syntax. They won't necessarily unearth problems in the code that cause implementation problems downstream, but they'll help catch other errors that might trip up synthesis. But linters are generally overlooked, Decker notes.
Also favoring code checkers is James Lee, president of the ASIC Group Inc., Fremont, Calif. "Code-checking and assertion-checking tools allow us to verify code without testbenches and simulation. They find bugs that would be annoying to find in simulation," says Lee.
In the past year, Lee and the ASIC Group have evaluated alternatives for ASIC synthesis and code-checking tools. "We now throw all new code through Real Intent's Verix property-checking tool before simulation and before signoff," says Lee. "I think it has helped us find bugs early."
Another way to approach RTL cleanup, but with an eye toward smoking out issues that will make implementation an endless loop of synthesis, placement, and routing iterations, is RTL rule checking. At Toshiba America Electronics Corp., RTL rule checking is an integral part of the front-end design cycle. In Toshiba's flow, when RTL handoff is called for, Toshiba's design-center engineers will rely on RTL rule checking to ensure that the code isn't harboring clocking or congestion problems.
"We use the Atrenta Spyglass RTL rule checkers as well as other similar tools," says Toshiba's Yamada. Toshiba uses the Atrenta tool with customized rule sets. "We have developed our own DFT (design-for-test) and clock-structure rules," he notes.
Toshiba also utilizes and has good success with Cadence's First Encounter for virtual prototyping. Using a gate-level netlist as input, First Encounter finds any rough spots in the design before moving on physical implementation. "With its high capacity, First Encounter can read in an entire netlist flat. It can do partitioning and initial placement so we can see whether we'll be able to achieve timing closure," says Yamada.