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Designers Pick EDA Favorites: Tools To Get It Right–Fast!
Engineers have a lot of positive things to say about the current state of the EDA industry, including some good ideas on how to improve tools.
Date Posted: February 16, 2004 12:00 AM
A WISH LIST
Today's tools have plenty of room for improvement, especially with 100- and 90-nm silicon processes on the horizon and 65-nm processes on the drawing boards. "Where I see the most difficulty at 65 nm is synthesis," says Kelly. "The way we do it today, taking a snapshot of the design in gates, won't work. Synthesis has to be more intelligent about finding the optimal point to fulfill all parameters."
Yamada sees weaknesses in the test area. "We are working hard to reduce test cost," he says. Toshiba is evaluating design-for-manufacturability (DFM) technologies to help in this regard. "Another area we have to consider in testing is at-speed testing," Yamada continues. "Currently, clock frequencies are exceeding the ATE (automatic-test-equipment) frequencies. So we need a special test technique for at-speed test during manufacturing. This is something we are lagging on."
Another lagging area is IC-package co-design, particularly for high-pin-count and flip-chip devices. "The implications of the package design can no longer be ignored for high-frequency, high-signal-count designs," says Parker. "Nor can a complicated silicon design be completed without regard to the package concerns."
Agere relies on a suite of internally developed co-design tools in its production flow. While this flow is effective today, it could gain efficiency by simplifying the interface and improving the sharing of data between the package and silicon design tools.
"We are working closely with our core EDA partners to improve this interface, but a transition to a pure commercial solution is some time off," Parker notes.
Many designers see problems in the area of power analysis. "As we go to on-chip voltages below 1 V, I don't see a good answer for transient IR-drop analysis," says Kelly. "There's a lot of work left to be done to determine current signatures for pieces of IP and how currents affect timing when voltages are that low. As accurate as models are getting, that's still an area where the industry needs to focus."