Your next system-on-a-chip (SoC) design will, in all likelihood, dissipate more power than your last one did. Even if you’ve topped out on core speed, chances are you’ll be adding functionality that will consume additional power. If you’re contemplating a move to a more advanced process technology, the increased leakage alone will cost you in terms of your power budget.
Power is the constraint du jour in chip design, and that’s reason enough to begin taking it much more seriously than ever before. If you’re truly serious about meeting your system power budget, a critical aspect of any portable or consumer design, you may want to begin thinking about power as early as you possibly can, and that means in the architectural definition phase of the project.
Power analysis and optimization at the electronic system level (ESL) isn’t yet part of mainstream design methodologies, but the day is rapidly approaching when it will be. This article will help you get up to speed with ESL power analysis and optimization, including what’s available for optimization of the RTL that you’ll feed into your synthesis flow.
WHY START ON POWER AT ESL?
The reasons for optimizing for power at ESL are many, but the simplest explanation is that you’ll get the biggest bang for your buck at higher levels of abstraction. “Lots of tools analyze power at RTL, which is good for determining whether you’re in spec,” says Brett Cline, vice president of marketing at Forte Design Systems. “But the changes you can make in RTL are very limited. You only have so many options there.”
Real power optimization happens at architecture level, says Cline. ESL synthesis tools can output RTL that is optimized for power. To be sure, designers can adopt best practices for RTL coding and use techniques such as clock gating to gain power reductions. “But realistically, someone needs to make smart architecture decisions to really reduce power,” says Cline.
“Most of a chip’s power consumption is determined in the architecture, RTL, and synthesis stage,” says Tom Sandoval, CEO of Calypto Design Systems. “Once synthesis has created a logic structure, the effects of subsequent changes on power are going to be small and incremental. Thus it is important to consider power during the logic design process.”
“Our real perspective is that the most important determiner of power is architecture,” says George Harper, vice president of marketing at Bluespec. “At that level, the extent to which you can explore the space, provide transparency, and facilitate the types of design choices is the best you can do for optimization of power in a chip design.”
Some EDA vendors claim that power savings of as much as 80% can be realized by tinkering at the architectural level. Yet often, they’re not telling you that this figure refers to savings compared with their own non-ESL flow. One can quibble over these numbers and how they are arrived at, but the point remains that you can’t do better later in the flow than you can at ESL (Fig. 1).
Architectural analysis and optimization carries multiple benefits in the power domain. The power savings are realized through optimization of the system architecture, not just for power but also for area and performance. The architecture level is also where designers can best address the partitioning of hardware and software. They can tune the application software to achieve best power consumption and also correlate power requirements with system workload.
The most common approach being used today for high-level power analysis and optimization is the virtual platform, or VP (see “Virtual Platform Technology 101”). Virtual platforms are a high-level representation of the system hardware that’s assembled from models typically written in C/C++ or SystemC.
Among those using ESL virtual platforms are system architects and software developers. Obviously, designers of portable systems are extremely concerned about system efficiency. “That isn’t just about how one particular hardware element might consume power, but how the different use cases of the product interact to consume power. That’s a system-level question, a software question, and a hardware question,” says Pat Sheridan, director of marketing at CoWare. ESL vendors such as Co-Ware and Carbon Design Systems market tools for the creation of virtual platforms.
Many designers are finding it useful to equip their virtual platforms to help measure power consumption. “Users are instrumenting VPs,” says Frank Schirrmeister, director of product marketing for system-level solutions at Synopsys. This entails using an existing VP in which designers have integrated various intellectual property (IP) blocks, including processor(s) and peripherals. As embedded software developers run their code on the platform, they can examine the power states of the blocks and annotate the VP with power-state information.
Texas Instruments has extensively used the Synopsys Innovator VP development environment for power modeling of its Open Multimedia Application Platform (OMAP) family. “We have done power modeling within the platform in which TI and their customers brought up the models. You can see the voltage regions within the chip and what happens if you drive the processors and peripherals to different states of load,” says Schirrmeister. “You can observe the external power-management IC and how it regulates the system voltage.”