THE IMPACT OF HIGH-LEVEL SYNTHESIS
Many users of high-level-synthesis (HLS) tools are coming to understand the true value of HLS in their flows. Like virtual platforms, HLS enables designers to explore multiple microarchitectures for optimizing QoR (Fig. 3).
In Calypto’s case, the company’s PowerPro MG, which automates memory power optimization, and its PowerPro CG, which performs broader RTL memory optimization, will soon include enhancements for designers in the process of hand-tweaking RTL. “We’ll give greater visibility into the RTL for designers who are creating the RTL by hand, either because it’s very high-performance circuitry or because they don’t want tools touching it,” says Sandoval.
Often, the RTL generated by HLS tools cannot be hand-optimized because it’s not readable by humans. “What the designer can do with HLS is build multiple high-level designs to figure out which gets best QoR, but he can’t go in and further modify it,” says Sandoval. Calypto’s Power CG and MG along with SLEC System-HLS, which independently verifies the HLS results, let them read that RTL and make sure they get the optimizations they seek (Fig. 4).
Another possibly more organic approach is that taken by ChipVision Design Systems, whose PowerOpt tool synthesizes power-optimized RTL directly from either ANSI C or SystemC code. “Since we already understood the power characteristics of the ESL model, we could implement an RTL version that minimized the power dissipation by minimizing both the area of the design, which is tied heavily to leakage, and the switching power, into which designers don’t have insight at RTL,” says Craig Cochran, ChipVision’s vice president of marketing and business development.
PowerOpt should be considered as a front end to RTL synthesis, says Cochran. Starting from C and synthesizing to RTL obviously saves the time and effort of hand-coding the RTL. But there’s the added benefit, says Cochran, of a much better RTL architecture. “When you have the opportunity to try many different architectural options, you end up with a better RTL starting point for the rest of the flow,” says Cochran.
PowerOpt does what all HLS tools do in terms of what-if analysis and rapid generation of multiple RTL architectures. It weighs all options to save area and/or increase speed such as pipelining and assorted memory architectures. But it adds a focus on power consumption by executing the C code with the user’s C testbench to measure switching activity. It then uses those measurements to guide switching minimization (Fig. 5).
Looking a little further under the hood, PowerOpt’s switching analyses emphasize mission modes and not corner cases to provide a true picture of power consumption in typical system operation. Switching activity data is compiled in a database that is accessed by the HLS engine. During synthesis, the tool compares various possible architectures and decides whether to map functions onto single resources, implement multiple resources, or instantiate pipelining.
“The tool comes up with some interesting tradeoffs,” says Cochran. “Generally, power tradeoffs are not very intuitive to users.” As the tool decides which architectures are most efficient, it looks into whether it should share registers and measures the impact that would have on power.
LIBRARY FOR PIPELINING
Bluespec is another HLS house with a path from high-level code to RTL. In this case, the code is Bluespec SystemVerilog (BSV). In an example of an 802.11a Wi-Fi transmitter design, the design team was able to use Bluespec’s simulator and compiler to implement seven different microarchitectures in just five man-days. Had the team followed the designer’s original intuition for the architecture, the device would have consumed an average of 34.6 mW. However, the architecture that was ultimately implemented consumed about 4 mW, albeit in considerably more area.
To augment its tools’ capabilities, Bluespec plans to offer a library of plug-and-play building blocks for pipelined architectures. The Pipeline Architecture Composers’ Library (PAClib) will enable designers to generate many different pipelined microarchitectures from a single source by simply dialing in parameters. The blocks, predesigned in BSV source code, let users separate the notion of architecture from the blocks’ computation function and from microarchitecture choice.
With the PAClib, designers write a single implementation and adjust parameters in an associated parameter file. “These can be thought of as Lego blocks for datapath pipelines,” says George Harper, Bluespec’s vice president of marketing. “They start from the premise that architecture is the primary driver of power consumption in chip design.” Because the blocks are so flexible in terms of parameters, they offer designers further opportunities for power savings.