There are a lot more FPGA design
starts these days than ASIC
design starts. But with FPGAs approaching the size and complexity of
ASICs, they bring along many of the
same verification issues. For many
FPGA designers, simulation is just too
slow and error-prone. Intellectual property (IP) behaves differently in simulation than it does on real hardware.
ASIC design works its way toward a
known-good chip by means of multiple
iterations of synthesis/place and route.
FPGA design, on the other hand, starts
with a known-good chip. That's what
startup GateRocket is exploiting in its
flagship product, the RocketDrive. RocketDrives take advantage of the actual
target FPGA to deliver simulation acceleration that ranges from a factor of 10 to
a factor of 100.
The RocketDrive is a hardware unit
that fits into a standard 5.25-in. PC
form factor. A PCI interface card and
software come with it. The system is
scalable to up to eight RocketDrives for
system-level verification. RocketDrives
are used to enhance existing verification flows using standard register-transfer-level (RTL) simulators from
vendors such as Cadence, Mentor
Graphics, and Synopsys.
In a typical simulation flow, the device
under test (DUT), testbench, IP, and custom logic are all run in the simulator
itself. But with a RocketDrive flow, any or
all of the parts of the FPGA design can
be run in the RocketDrive on the native
device (). Currently, GateRocket supports the Altera Stratix-II and
Xilinx Virtex-4 families, with support for
the Stratix-III and Virtex-5 devices coming later this year.
The "device-native" approach used in
RocketDrives gets around the need that
arises in traditional emulation environments to map the DUT into proprietary
hardware. Rather, the actual FPGA that will
be used in the end product is linked with
the software simulation environment.
RocketDrives for the Altera Stratix-II
and Xilinx Virtex-4 FPGA families are
available now. Pricing starts at $25,000.
GateRocket Inc.
www.gaterocket.com