Designers must adopt new methodologies to capitalize on the benefits of cycle-based simulators. This methodology shift will not happen in the foreseeable future. As a result, giving attention to Spice-like accuracy in digital simulators remains important. Hardware accelerator and emulator companies and vendors of fast event-based simulators, such as Cadence, Avant!, Viewlogic, Mentor, and Model Technology, are banking on the fact that most designers are not going to—or may not be able to—change their design styles to fully synchronous ones, and thus will require fast event-based simulators.
Vendors of hardware emulators and hardware accelerators build special-purpose hardware that can achieve 10X to 100X performance at system and ASIC verification levels, yet maintain event-based accuracy. The demand has increased for these high-performance hardware and software solutions, a good indication that the requirement for event-simulation accuracy is alive and well. The design community must change design styles for the paradigm shift to the cycle-based/static timing verification approach to be successful.
Unlike event-based timing simulators, static timing tools do not require a set of stimulus to provide an indication of the circuit's timing. They do require the design to be fully synchronous for the results to be accurate. The purpose of these tools is to ensure that all device propagation activity occurs within a clock cycle. When asynchronous logic exists in the design, the tool cannot detect possible race conditions that can cause a glitch in the circuit and possible malfunction. Event-based simulators can provide full coverage of both timing and functionality including races, and glitches; providing they are given a complete set of input stimulus. Since it may not be possible to provide complete stimulus coverage, especially in large complex designs, static timing can provide additional verification protection.
Design Flows
Engineers need to evaluate each of the available design tools in conjunction with their design methodology and styles to determine a proper fit. In some cases, it may be necessary to alter current design methodologies to match the capabilities of the tool. Where adequate tools aren't available, users (especially silicon vendors) may be forced to develop the capability "in-house" where the silicon expertise resides. This also can create a tighter coupling between the process and tools as well as tool-to-tool integration. Using commercial solutions still remains a better solution where possible, even though the cost of integrating them into a given flow can be high in terms of time and money.
The one area where a company's design methodology may vary is the high-level design entry point, i.e., behavioral or data flow (RTL). This often depends on the application and the engineering expertise within the company. Hardware/software co-verification and full system verification also may dictate at which level to begin. Until recently, all behavioral representations of the design had to be "human-synthesized" due to the lack of available tools to perform the task. Some limited behavioral synthesis tools are now available, and it is expected that similar capabilities to those offered by RTL synthesis tools will be available as these products mature.
At the behavioral or RTL level, there's no real need for the accuracy of event-driven simulation, thus using a cycle-based simulator will provide adequate functional verification. The designs need to be split into approximately 10-kgate blocks to meet the limitations of most synthesis tools, however newer products on the market are claiming greater capacity. Configuration files are used to specify timing, power, and any other special requirements of the design.
Formal verification can be an excellent way to perform early design verification between this new structural representation of the design against its RTL predecessor. Design for test also must be considered at this point since testing of these large complex devices is becoming increasingly difficult and time consuming. Built-in self test (BIST) is now being considered for the entire ASIC due to testing complexities and time to validate production units. This is particularly applicable to complex IPs.
Once the design is synthesized into structural blocks, it can be subjected to analysis tools such as dynamic simulation, power analysis, and static timing. At this point, it's important to know if the design meets the criteria for fully synchronous designs. Some ASIC vendors like AMI have tools that analyze the design for not only design problems, but also to determine its compliance with fully synchronous design styles. For designs that meet the criteria, cycle-based simulation and static timing analysis can provide adequate validation.
For designs that do not, cycle-based simulators may still be an option for early validation, followed by full event simulation verification before releasing the design to the ASIC vendor. Since wire interconnect is a dominant part of the overall delay, floorplanners must become an integral part of the early synthesis steps as well as pre and post layout if design iterations are to be minimized. This applies to not only event-driven simulators, but also to static timing, and power- and noise-analysis tools.
The final sign-off validation requirements are still in the hands of the ASIC foundry which is responsible for ensuring the design is manufacturable. In the past, most ASIC vendors had either an internal proprietary "golden" simulator or used a commercial tool they trusted for final verification of the design. Now with the emergence of the HDL standards, most are providing sign-off support for various simulators that they have certified to be in compliance with the standards. With this in place, qualified customers can now perform the sign-off registration at their facility instead of passing off the design to the foundry, where registration differences may be found between the simulator the customer used versus the internal "golden" simulator. This puts the onus on the standards committees to ensure these languages are equal to the task.
What's Next?
Each new generation of technology will continue to bring with it new challenges that will likely require additional standards. One thing we must not do is to allow the release of standards to impact our ability to move forward. Both HDL language standards committess are preparing for a 1998 reballot. Silicon and tool vendors must work closely with the standards committees to ensure the standards keep pace.
Integrating the various EDA tools in a cohesive tightly coupled design environment may not be enough to ensure success. Silicon vendors may need to develop internal tools to augment those offered commercially. If the past 15 years are any indication of what this industry can do, the future looks bright as long as the team is working together.