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EDA Alert: December 19, 2006


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============================================


EDA Alert e-Newsletter
Electronic Design -- www.electronicdesign.com
December 19, 2006

=======================================



Today's Table of Contents:

1. Viewpoint: Newer Hardware Acceleration and Verification Systems
Bringing Something New to the Table
2. Fill-Synthesis Tool Counterbalances CMP Steps
3. RF Designers Gain Signal-Integrity Models
4. OPC Tool Spurred By Cell-Processor-Based Hardware
5. Book Review: System-Level Design With Rosetta
6. Happenings
- ThETA'07
- VLSI'07
- ASPDAC'07
- FPGA'07

************
1. Viewpoint -- Exclusive to EDA Alert
************
Newer Hardware Acceleration and Verification Systems Bringing
Something New to the Table

Ping-Sheng Tseng, Cadence Fellow
Cadence Design Systems Inc., San Jose, Calif.

Hardware-based verification systems have seriously outgrown their
reputation of a few years ago. They are no longer those behemoth boxes
that sit in the corner of the lab for use only by a select few. They
are becoming much more widely available and user-friendly-and not just
for those that can afford such verification horsepower...

Read the complete story at:
Viewpoint ==>
http://news.electronicdesign.com/t?ctl=43FFF:8857EF

*******
2. News
*******
Fill-Synthesis Tool Counterbalances CMP Steps

It's critical that the surface of silicon wafers be as flat as
possible so that as each metal layer is patterned, you minimize the
risk of moving in and out of the focal plane of the imaging system.
Failure to achieve near-perfect flatness can result in
yield-destroying parametric failures...

Read the complete story at:
http://news.electronicdesign.com/t?ctl=44000:8857EF

*******
3. News
*******
RF Designers Gain Signal-Integrity Models

Modeling of the signal distortion that occurs when high-speed ICs are
connected to backplanes and PC boards is made easier through use of
The MathWorks' RF Toolbox 2, a set of functions that's based on the
Matlab modeling environment. The functions enable users to design,
model, analyze, and visualize the networks of RF components typically
found in high-speed data transmission...

Read the complete story at:
http://news.electronicdesign.com/t?ctl=44001:8857EF

*******
4. News
*******
OPC Tool Spurred By Cell-Processor-Based Hardware

The next generation of Mentor Graphics' optical-proximity correction
(OPC) tool has arrived, bringing with it a number of innovations that
result in improved simulation accuracy. Calibre nmOPC is a
third-generation OPC tool that takes on the complexity of
reticle-enhancement technologies that 45-nm processes will usher in...

Read the complete story at:
http://news.electronicdesign.com/t?ctl=43FFD:8857EF

**************
5. Book Review
**************
System-Level Design With Rosetta
By Perry Alexander
ISBN: 978-1-55860-771-2

The design of a system is rarely, if ever, accomplished with all
aspects of that system described in the same fashion. For example, an
automobile brings together design work from a number of discrete
disciplines and domains-mechanical, electrical, ergonomic, and even
economic, to name but a few...

Read the complete story at:
http://news.electronicdesign.com/t?ctl=43FFE:8857EF

*********************************************
TAKE A POLL: In his Editor's Note, Lou Frenzel suggests that cellular
carriers will probably never offer dual-mode phones. What do you
think?

-- Agree: Given their Wi-Fi capabilities, dual-mode phones would hurt
business
-- Disagree: Carriers could lure business from competitors with these
phones
-- Unsure: It's too early to say if a viable business model is
feasible

Electronic Design's Quick Poll ==>
http://news.electronicdesign.com/t?ctl=44007:8857EF

*********************************************
**************
6. Happenings
**************
Int'l Conference on Thermal Issues in Emerging Technologies: Theory
and Applications (ThETA'07)
Cairo, Egypt
Jan 3-6, 2007
http://news.electronicdesign.com/t?ctl=44008:8857EF

Int'l Conference on VLSI Design (VLSI'07)
Bangalore, India
Jan 6-10, 2007
http://news.electronicdesign.com/t?ctl=44004:8857EF

Asia and South Pacific Design Automation Conference (ASPDAC'07)
Yokohama, Japan
Jan 23-26, 2007
http://news.electronicdesign.com/t?ctl=44006:8857EF

Int'l Symposium on Field-Programmable Gate Arrays (FPGA'07)
Monterey, Calif.
Feb 18-20, 2007
http://news.electronicdesign.com/t?ctl=44003:8857EF

*******************************************************
EDA ALERT e-NEWSLETTER CONTACTS

====================================
EDA Technology Editor, Electronic Design: David Maliniak
mailto:dmaliniak@penton.com

Advertising/Sponsorship Opportunities: Bill Baumann
mailto:bbaumann@penton.com

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Electronic Design subscriber, or should be (145,000 of your peers
are). To apply for or renew a subscription to Electronic Design
absolutely FREE and without paperwork or hassle, click on the link
below.
http://news.electronicdesign.com/t?ctl=44002:8857EF


Copyright 2006 Penton Media, Inc. All rights reserved.

Electronic Design
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