Today's Table of Contents:
1. Viewpoint Exclusive -- Improve DFM By Using Experimental Measurements
2. SystemC Development Package Won't Break The Bank
3. Try Product Lifecycle Management Tool With Little Risk
4. Free Simulator Sees Upgrades
5. Design Tool Adheres To IP-Packaging Specs
6. Embedded-Software Accelerator Validated In RTL Flow
7. Happenings
- Design & Verification Conference (DVCon 2005)
- International Symposium on Field-Programmable Gate Arrays
(FPGA 2005)
- ACM/IEEE International Workshop on Timing Issues in the
Specification and Synthesis of Digital Systems (TAU 2005)
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1. Viewpoint -- Exclusive to EDA Alert
************
Improve DFM By Using Experimental Measurements
Tim Crandle, President
Stone Pillar Technologies, Santa Clara, Calif.
More aggressive silicon yield ramps, shrinking geometries, and more
complex analog/mixed-signal process flows have placed a stronger focus
on design for manufacturability (DFM) as an underlying design concept.
Proposed approaches to DFM typically involve specific design techniques
that will improve the likely yield of a particular design. But to reduce
systematic defects will require better visibility into key attributes of
critical processing steps at all stages of a yield ramp. Process and
device technology development groups must retain information from early
stages of technology development for subsequent yield improvement
efforts. Plus, they need information that will help them understand the
manufacturing impact of their decisions, as well as the effect of
technology improvements on final product yield.
Both technology development and design disciplines need access to a
data-management system that collects the data required to make design
and manufacturing decisions. Many technology development groups have
developed such data-management systems, but they tend to span either
design or technology development, not both. The result is narrowly
focused analyses when attempting to tackle yield or manufacturability
issues. Manually creating connections between pieces of data after an
issue arises is error-prone, and small errors in data assembly can lead
to incorrect conclusions.
To maximize the return on investment in test chips, experimental split
lots, and electrical test measurements, employ an approach that
facilitates the retention of details about process technology
development from the start. To avoid relying on isolated "silos of
information" residing with different engineering disciplines, technology
development engineers need a common data repository. However, data
collection alone is insufficient. The data within the repository must be
structured and interrelated to make it useful to all, both for the
current design and for future iterations.
The disconnect between manufacturing and design often comes down to an
inability to easily access the same information within a timeframe
useful for discussion and analysis. Engineers must be able to analyze
both process parameters and design parameters on an equal footing. For
instance, the optimum tradeoff between performance, real estate, and
yield for threshold voltage might be achieved by optimizing with respect
to both threshold-adjust implant dose AND p-well/composite overlap rule.
To make sense of these two disparate inputs in the design and process
technology equation will take side-by-side analysis.
In the current technology development process, many have lost a full
appreciation of the most important IP produced during technology
development: experimental measurements on test device designs. Such data
must be given the respect that their inherent cost to produce deserves.
Maximum value can be extracted from this data only by retaining all
aspects of the process and design parameters for subsequent analysis.
For instance, technology development groups should set initial
electrical performance targets for supported devices. Then they should
archive these within a common repository that will be interconnected
with downstream attributes, such as test structure layouts and design
rules. After that, connect individual devices directly to applied tests
as well as subsequent electrical test results. Ideally, this information
also should be interconnected with experiment designs and process flow
revisions. This interconnection enables the effects of any of these
variations to be analyzed while examining possible ways to improve
manufacturability.
A common data repository and management system offers easy access to,
and manipulation of, process and design details. Therefore, members of
different groups can communicate in a common language about results they
are analyzing. The ability to share details in this manner provides an
unambiguous basis for selection of optimal process flows or device
designs.
Using a central data-management system to focus all engineering
disciplines on experimental measurements of test device designs can
speed up technology development, reduce engineering cost, minimize
errors, and provide greater insight into all phases of technology
development. Centralized data management also extends the use of data
produced during the technology development stage for application in
yield-improvement studies. Furthermore, a well-implemented
data-management system inherently automates time-critical and
error-prone steps, such as test-chip, test-plan, and experiment
documentation.
Technology development produces volumes of measured data. That data must
be organized in a fashion useful to all disciplines, for the current
design and for future designs and iterations. Maximizing the value of
the investment in technology development for design- and
manufacturing-focused DFM requires exploiting experimental data
throughout all stages of a technology's lifecycle, from technology
development through yield improvement.
Contact Tim Crandle at: mailto:tcrandle@stonepillar.com
To comment on this Viewpoint, go to Reader Comments at the foot of the
Web page:
EDA Alert ==>
http://nls.planetee.com/t?ctl=61B:F3222
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2. News
*******
SystemC Development Package Won't Break The Bank
The SystemCrafter package for SystemC development work comes at
relatively low cost, giving designers an opportunity to experiment with
algorithmic-level modeling of hardware and software. The package
consists of the SystemCrafter SC compiler for synthesis of SystemC to
VHDL, plus the ZestSC1 FPGA development board. The compiler sells for
$995, the board starts at $495, and the package of compiler and
development board starts at $1490.
SystemCrafter SC automatically synthesizes hardware designs written in
SystemC to VHDL, which can then be used with widely available tools to
target Xilinx FPGAs. The ZestSC1 desktop FPGA development board, from
Orange Tree Technologies, sports a 480-Mbit/s USB interface for quick
FPGA programming.
The package can be purchased online from Orange Tree Technologies. A
free evaluation version of SystemCrafter SC can be downloaded and used
for 30 days.
Orange Tree Technologies ==> http://nls.planetee.com/t?ctl=622:F3222
SystemCrafter ==> http://nls.planetee.com/t?ctl=624:F3222
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3. News
*******
Try Product Lifecycle Management Tool With Little Risk
In a major initiative to accelerate adoption of product
lifecycle-management (PLM) software, Arena Solutions is offering its
Arena PLM Workgroup Edition, an entry-level version of its PLM software,
at no cost for the first year. Designed for teams of five or fewer, the
Workgroup Edition offers full-featured product record-management
functionality bundled with online tutorials, sample data sets, and full
customer support.
The tool can be ordered immediately at the company's Web site. Following
the one-year free subscription period, the Workgroup Edition can be
renewed for $2500 per year for up to five users.
Arena Solutions ==> http://nls.planetee.com/t?ctl=623:F3222
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4. News
*******
Free Simulator Sees Upgrades
An enhanced version of Ansoft's Maxwell SV (student version) adds a 2D
electric field solver, 2D dc and ac magnetic solvers, and improved
post-processing capabilities. Maxwell SV is a free, downloadable subset
of Maxwell 2D, which is the company's commercial electromagnetic-field
simulator.
Maxwell SV offers the same unrestricted, 2D field solvers that are
available in the commercial edition. To learn more about Maxwell 2D,
visit: http://nls.planetee.com/t?ctl=61D:F3222
Ansoft ==> http://nls.planetee.com/t?ctl=621:F3222
*******
5. News
*******
Design Tool Adheres To IP-Packaging Specs
Release 2.2 of Prosilog's Magillem platform-based design tool includes
the Spirit Editor module, which allows IP blocks to be packaged
according to the recently released SPIRIT 1.0 specification. Designers
can import and instantiate their SPIRIT-compatible IP blocks in
Magillem. Then, after construction of the platform, the design netlist
can be exported either in VHDL/Verilog or in the SPIRIT format.
Prosilog ==> http://nls.planetee.com/t?ctl=629:F3222
SPIRIT Consortium ==> http://nls.planetee.com/t?ctl=620:F3222
*******
6. News
*******
Embedded-Software Accelerator Validated In RTL Flow
A benchmark project found success in validating CriticalBlue's Cascade
tool with respect to Synopsys' RTL implementation flow. Working with a
large semiconductor company that defined the embedded software benchmark
example and its target gate count and performance constraints, Cascade
determined the available space for the resulting coprocessor and
generated synthesizable RTL for a suitable coprocessor architecture. No
modifications were made to the original embedded software.
Synopsys' Design Compiler and VCS verification suite were used to
synthesize and validate the output from Cascade. The tool delivered the
predicted gate count and performance specs for 130-nm technology.
The benchmark project involved an open-source embedded software
implementation of a BCH error-correction algorithm typically used in
wireless applications.
CriticalBlue ==> http://nls.planetee.com/t?ctl=626:F3222
Synopsys ==> http://nls.planetee.com/t?ctl=627:F3222
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7. Happenings
**************
Design & Verification Conference (DVCon 2005)
Doubletree Hotel, San Jose, Calif.
Feb. 14-16, 2005
http://nls.planetee.com/t?ctl=62B:F3222
International Symposium on Field-Programmable Gate Arrays (FPGA 2005)
Hyatt Regency Hotel, Monterey, Calif.
Feb. 20-22, 2005
http://nls.planetee.com/t?ctl=62A:F3222
ACM/IEEE International Workshop on Timing Issues in the Specification
and Synthesis of Digital Systems (TAU 2005)
Crowne Plaza Union Square, San Francisco, Calif.
February 28 - March 1, 2005
http://nls.planetee.com/t?ctl=625:F3222
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