EDA Alert: February 6, 2007

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EDA Alert e-Newsletter
Electronic Design -- www.electronicdesign.com
February 6, 2007

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Today's Table of Contents:

1. Viewpoint: Speeding To A Verification Answer
2. Processor Designer Improves Support For VLIW Processors
3. Simulation Technology Spices Up High-Speed Digital PCB Design
4. IEEE Approves Variation-Aware Extension To SPEF Format
5. Book Review: History of Semiconductor Engineering
(Reviewer: Bob Pease)
6. Happenings
- FPGA'07
- DVCon
- DATE (Design, Automation, and Test in Europe)

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1. Viewpoint -- Exclusive to EDA Alert
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Speeding To A Verification Answer

John Gallagher, Senior Director of Outbound Marketing
Synplicity Inc., Sunnyvale, Calif.

While there have been some recent improvements in RTL verification technology, today's reality is that hardware-based approaches are needed to verify RTL against real-world system conditions. Lots of R&D is ongoing, but a solution is not expected any time soon...

Read the complete story at:
Viewpoint ==> http://www.elecdesign.com/Articles/ArticleID/14831/14831.html

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2. News
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Processor Designer Improves Support For VLIW Processors

CoWare's latest Processor Designer release boosts support for next-generation VLIW processors. Processor Designer enables users to explore a large design space to ensure that the targeted processing power is achieved and the interconnect infrastructure is available to feed data into the processor at an acceptable rate...

Read the complete story at:
http://www.elecdesign.com/Articles/ArticleID/14832/14832.html

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3. News
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Simulation Technology Spices Up High-Speed Digital PCB Design

Agilent claims a breakthrough for achieving accurate response in time-domain simulators when it comes to pcb interconnects at data rates of more than 1 Gb/s -- enter the Signal Integrity Designer Premier suite...

Read the complete story at:
http://www.elecdesign.com/Articles/ArticleID/14833/14833.html

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4. News
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IEEE Approves Variation-Aware Extension To SPEF Format

The IEEE 1481 Working Group has approves Synopsys' proposal for an extension to the Standard Parasitic Exchange Format (SPEF) for process and temperature variation, enhancing the existing IEEE Standard 1481-1999 for SPEF...

Read the complete story at:
http://www.elecdesign.com/Articles/ArticleID/14834/14834.html

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5. Book Review
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History of Semiconductor Engineering
By Bo Lojek
ISBN: 3540342575

Once upon a time, if you wanted to make a junction transistor, you could start with a small seed crystal of pure germanium. Using Czochralski's 1917 methods, the crystal was gradually rotated and pulled out of a lightly doped N-type material and grown into a small boule...

Read the complete story at:
http://www.elecdesign.com/Articles/ArticleID/14727/14727.html

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TAKE A POLL: In a recent editorial, Lou Frenzel says that there is a real need for a good networking technology that can handle video. Which technology do you think has potential?

-- Wi-Fi
-- 802.11n
-- Ultra wideband (UWB)
-- WirelessHD
-- A combination of two or more technologies
-- None of these

Electronic Design's Quick Poll ==> http://www.elecdesign.com/#poll

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6. Happenings
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Int'l Symposium on Field-Programmable Gate Arrays (FPGA'07)
Monterey, Calif.
Feb. 18-20, 2007
http://conferences.ece.ubc.ca/isfpga2007/

DVCon
Santa Clara, Calif.
Feb. 21-23, 2007
http://www.dvcon.org

DATE (Design, Automation, and Test in Europe)
Nice, France
April 16-20, 2007
http://www.date-conference.com/

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EDA ALERT e-NEWSLETTER CONTACTS

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EDA Technology Editor, Electronic Design: David Maliniak
mailto:dmaliniak@penton.com

Advertising/Sponsorship Opportunities: Bill Baumann
mailto:bbaumann@penton.com

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