EDA Alert: October 21, 2002

==================================

EDA Alert e-Newsletter
PlanetEE - www.planetee.com
October 21, 2002

=============================

*************************ADVERTISEMENT***************************
Free Demo and Presentation - Co-verification for platform FPGAs
* Why co-verification for development of systems using
Platform FPGAs?
* Platform FPGAs - design solution for broad range of
applications
* Design tools and flows for Virtex-II Pro(tm)
* Key features of Virtex-II Pro(tm)
Register today:
http://lists.planetee.com/cgi-bin3/flo?y=eN2s0DJhFR0BSK05ce0A4
*****************************************************************

You've received this e-newsletter for one of three reasons:
1) you received our EDA Alert newsletter in the past,
2) you've signed up for it at http://www.planetee.com, or
3) you've identified yourself as a specifier of EDA tools on
your qualification form as a reader of Electronic Design
Magazine.

Please see below for unsubscribe and address-change instructions.


Today's Table of Contents:
1. Viewpoint - Is Analog The Monkey Wrench In The Works For
RTL ASIC Signoff?
2. Agilent Updates Its RF Design Suite
3. Accellera Elects New Officers
4. Coolsand Turns To Axis For High-Level Verification
5. Tensilica Unveils New Instruction Set Architecture
6. Happenings
IEEE International High Level Design Validation And Test
Workshop
IP-Based SOC Design Workshop
IEEE International Conference on Computer-Aided Design (ICCAD)
Conference on Design of Circuits and Integrated Systems (DCIS)
DesignCon 2003
Design and Verification Conference and Exhibition
(DVCon, formerly HDLCon)


************
1. Viewpoint
************
Is Analog The Monkey Wrench In The Works For RTL ASIC Signoff?
By David Maliniak, EDA Technology Editor

It's obvious that a change is afoot in ASIC handoff. The
traditional model, with its split between front- and back-end
design at the gate-level netlist following logic synthesis,
is being blown out of the water by process shrinks to 130 nm
and smaller. It's exciting to watch the industry gear up
with a new generation of tools that endeavor to bring much more
physical information than ever before into the "front end" of
the ASIC design process.

So the point at which designs are "thrown over the wall" to
those who would perform physical implementation (legal floorplan,
placement and routing) is changing, and change it must. Some
would have it move lower in abstraction, i.e. GDSII (or its
apparent successor, the Universal Data Model, being developed
under the aegis of the Semiconductor Equipment and Materials
International). Others see benefits to moving handoff upward in
abstraction to register-transfer level (RTL).

There's other trends in design, however, that could mitigate
against RTL as a handoff point. The one that comes to mind is the
fast-growing analog/mixed-signal (A/M-S) content being
incorporated into ASICs. According to Jue-Hsien Chern, vice
president and general manager of Mentor Graphics's DSM division,
the rub lies in the fact that most A/M-S intellectual property
isn't synthesizable but rather comes to the designer in the form
of GDSII. This mix of abstraction levels means that until there's
sufficient confidence in the precision of RTL models, the handoff
point will continue to vary from design to design.

"The 'big' prediction of RTL handoff, etc. is not moving as fast
as predicted," comments Dennis Brophy, director of strategic
business development for Model Technology. "As such, functional
verification at the gate-level will remain critical. In some
cases, the current gate-level implementations are beginning to
fail in wire-dominated designs as found in sub-130-nm design."

Chern sees increased reliance on A/M-S extensions to Verilog and
VHDL. "We observed this trend starting in Europe but it's also
now emerging in the U.S. and Japan," said Chern. Use of VHDL-AMS
or Verilog-AMS for modeling of A/M-S blocks would, theoretically,
restore the ability to perform a top-level Verilog or VHDL type
of design.

"We would be thrilled if the industry found a way to decrease its
dependence on gate-level design and move to RTL and
behavioral-dominated design analysis," said Brophy. "Until the
industry moves in such a direction, however, we continue to
support the needs of an industry destined to find 50-million-gate
designs common in the near
future."

I'd be more than interested in hearing of your experiences with
A/M-S IP blocks in ASIC design and how they've affected the
verification process. In fact, you can share your thoughts with
each other by posting to our bulletin boards at
http://www.planetee.com/forums/.

And look for a special report on ASIC handoff and methodology
trends in an upcoming issue of Elecronic Design Magazine.

Write me at: dmaliniak@penton.com

*******
2. News
*******
Agilent Updates Its RF Design Suite
The latest version of Agilent's ADS 2002C design tools for RF,
microwave and wireless communication products brings upgrades in
simulation technology and usability for RF system, circuit and
physical design. Advances in the software over the previous
release include a multi-threaded Agilent Ptolemy simulation, a
TD-SCDMA Design Library and a link to Agilent's ESG Signal Studio
software.

Agilent ADS 2002C is equipped with a new feature that adds
circuit and physical co-optimization to co-simulation with layout
components introduced earlier this year. The new feature allows
ADS to adjust both circuit component values and layout dimensions
to optimize physical and circuit performance. The co-optimization
with layout components feature uses ADS' EM simulator, Momentum,
and features including RF mode for fast analysis of electrically
small circuits and arbitrary polygonal mesh for high levels of
accuracy and speed. The suite is available now. Prices start at
$8,400.
http://eesof.tm.agilent.com/

*******
3. News
*******
Accellera Elects New Officers
Accellera, the electronics industry organization focused on
language-based design standards, today announced that its Board
members(systems, semiconductor and design tool companies) have
elected a new slate of officers. Dennis Brophy, director of
strategic business development at Model Technology, was elected
Accellera's chair for a third term. Shrenik Mehta, senior
engineering manager, Sun Microsystems, was elected vice chair.
Steve Wang, vice president and co-founder, Axis Systems, was
elected treasurer. Karen Bartleson, director of quality and
interoperability, Synopsys, was re-elected secretary for a third
term.
http://www.accellera.org/


*******
4. News
*******
Coolsand Turns To Axis For High-Level Verification
Coolsand Technologies Inc., Paris, France, has chosen Axis
Technology's Xtreme verification system and is using it early in
the design flow to verify the architecture of a system-on-a-chip
(SoC) for the portable multimedia consumer electronics market.

Coolsand's multimedia chip is a complex, highly integrated SoC.
The main reason Coolsand needed Xtreme so early in the flow was
to run the millions of simulation cycles needed to verify the
performance and interoperability of computation-intensive
multimedia functions mapped in hardware. Architectural
verification was accomplished very early, running C code on the
Axis system. Axis introduced its language-neutral verification
platform in March 2002. The newest versions of Axis' Xcite and
Xtreme verification systems support both VHDL and Verilog with no
restrictions between language boundaries. During simulation,
acceleration, and emulation, customers now can arbitrarily mix
both languages in the same design, and debug any signal within
that design -- whether it's a VHDL or Verilog signal.
http://www.axiscorp.com/

*******
5. News
*******
Tensilica Unveils New Instruction Set Architecture

In previewing the next generation of its Xtensa processor ISA
(instruction set architecture) at last week's Microprocessor
Forum, Tensilica Inc.'s chief architect, Bill Huffman, covered
ideas for a long instruction word format for designer-defined
instructions that has many of the benefits of VLIW (performance)
but none of the drawbacks (code bloat). Tensilica calls this
configurable architecture FLIX for Flexible Length Instruction
Xtensions.

The FLIX capabilities will allow designers to add custom TIE
(Tensilica Instruction Extension) language instructions that use
longer word lengths to achieve greater parallelism and higher
performance. FLIX will allow a modeless mix of 16-, 24-, and
64-bit instructions so code can be fast and parallel when needed
or compact when parallelism isn't needed. Using the TIE
language, designers can develop an
unlimited variety of designer-defined instructions for
applications ranging from communications processors to consumer
multimedia. The FLIX-enhanced ISA will be fully upwards
compatible with all current Xtensa processor configurations.
http://www.tensilica.com/

*************
6. Happenings
*************

IEEE International High Level Design Validation And Test Workshop
Côte d'Azur, Cannes, France
October 27-29, 2002
http://lists.planetee.com/cgi-bin3/flo?y=eN2s0DJhFR0BSK05Ar0Ai

IP-Based SOC Design Workshop
Espace Congres du World Trade Center, Grenoble, France
October 30-31, 2002
http://lists.planetee.com/cgi-bin3/flo?y=eN2s0DJhFR0BSK05cl0AC

IEEE International Conference on Computer-Aided Design (ICCAD)
Doubletree Hotel, San Jose, CA
November 10-14, 2002
http://lists.planetee.com/cgi-bin3/flo?y=eN2s0DJhFR0BSK05As0Aj

Conference on Design of Circuits and Integrated Systems (DCIS)
Palacio de la Magdalena, Sanstander, Spain
November 19-22, 2002
http://lists.planetee.com/cgi-bin3/flo?y=eN2s0DJhFR0BSK05cm0AD

DesignCon 2003
Santa Clara Convention Center, Santa Clara, CA
January 27-30, 2003
http://lists.planetee.com/cgi-bin3/flo?y=eN2s0DJhFR0BSK05cn0AE

Design and Verification Conference and Exhibition (DVCon,
formerly HDLCon)
Doubletree Hotel, San Jose, CA
February 24-26, 2003
http://lists.planetee.com/cgi-bin3/flo?y=eN2s0DJhFR0BSK05co0AF

EDA ALERT e-NEWSLETTER CONTACTS

===============================

EDA Technology Editor, Electronic Design: David Maliniak
mailto:dmaliniak@penton.com

Advertising/Sponsorship Opportunities:
Bill Baumann, bbaumann@penton.com

=========================

To subscribe send a blank email to:
mailto:EDA_Alert_Sub@lists.planetee.com
To unsubscribe send a blank email to:
mailto:EDA_Alert_Unsub@lists.planetee.com
Penton's e-Newsletter homepage:
http://lists.planetee.com/cgi-bin3/flo?y=eNOj0DJhFR0C4C0Jvu0Ah

===============================
Copyright 2002 Penton Media Inc.

==================================

EDA Alert e-Newsletter
PlanetEE - www.planetee.com
October 21, 2002

=============================

*************************ADVERTISEMENT***************************
Free Demo and Presentation - Co-verification for platform FPGAs
* Why co-verification for development of systems using
Platform FPGAs?
* Platform FPGAs - design solution for broad range of
applications
* Design tools and flows for Virtex-II Pro(tm)
* Key features of Virtex-II Pro(tm)
Register today:
http://lists.planetee.com/cgi-bin3/flo?y=eN2s0DJhFR0BSK05ce0A4
*****************************************************************

You've received this e-newsletter for one of three reasons:
1) you received our EDA Alert newsletter in the past,
2) you've signed up for it at http://www.planetee.com, or
3) you've identified yourself as a specifier of EDA tools on
your qualification form as a reader of Electronic Design
Magazine.

Please see below for unsubscribe and address-change instructions.


Today's Table of Contents:
1. Viewpoint - Is Analog The Monkey Wrench In The Works For
RTL ASIC Signoff?
2. Agilent Updates Its RF Design Suite
3. Accellera Elects New Officers
4. Coolsand Turns To Axis For High-Level Verification
5. Tensilica Unveils New Instruction Set Architecture
6. Happenings
IEEE International High Level Design Validation And Test
Workshop
IP-Based SOC Design Workshop
IEEE International Conference on Computer-Aided Design (ICCAD)
Conference on Design of Circuits and Integrated Systems (DCIS)
DesignCon 2003
Design and Verification Conference and Exhibition
(DVCon, formerly HDLCon)


************
1. Viewpoint
************
Is Analog The Monkey Wrench In The Works For RTL ASIC Signoff?
By David Maliniak, EDA Technology Editor

It's obvious that a change is afoot in ASIC handoff. The
traditional model, with its split between front- and back-end
design at the gate-level netlist following logic synthesis,
is being blown out of the water by process shrinks to 130 nm
and smaller. It's exciting to watch the industry gear up
with a new generation of tools that endeavor to bring much more
physical information than ever before into the "front end" of
the ASIC design process.

So the point at which designs are "thrown over the wall" to
those who would perform physical implementation (legal floorplan,
placement and routing) is changing, and change it must. Some
would have it move lower in abstraction, i.e. GDSII (or its
apparent successor, the Universal Data Model, being developed
under the aegis of the Semiconductor Equipment and Materials
International). Others see benefits to moving handoff upward in
abstraction to register-transfer level (RTL).

There's other trends in design, however, that could mitigate
against RTL as a handoff point. The one that comes to mind is the
fast-growing analog/mixed-signal (A/M-S) content being
incorporated into ASICs. According to Jue-Hsien Chern, vice
president and general manager of Mentor Graphics's DSM division,
the rub lies in the fact that most A/M-S intellectual property
isn't synthesizable but rather comes to the designer in the form
of GDSII. This mix of abstraction levels means that until there's
sufficient confidence in the precision of RTL models, the handoff
point will continue to vary from design to design.

"The 'big' prediction of RTL handoff, etc. is not moving as fast
as predicted," comments Dennis Brophy, director of strategic
business development for Model Technology. "As such, functional
verification at the gate-level will remain critical. In some
cases, the current gate-level implementations are beginning to
fail in wire-dominated designs as found in sub-130-nm design."

Chern sees increased reliance on A/M-S extensions to Verilog and
VHDL. "We observed this trend starting in Europe but it's also
now emerging in the U.S. and Japan," said Chern. Use of VHDL-AMS
or Verilog-AMS for modeling of A/M-S blocks would, theoretically,
restore the ability to perform a top-level Verilog or VHDL type
of design.

"We would be thrilled if the industry found a way to decrease its
dependence on gate-level design and move to RTL and
behavioral-dominated design analysis," said Brophy. "Until the
industry moves in such a direction, however, we continue to
support the needs of an industry destined to find 50-million-gate
designs common in the near
future."

I'd be more than interested in hearing of your experiences with
A/M-S IP blocks in ASIC design and how they've affected the
verification process. In fact, you can share your thoughts with
each other by posting to our bulletin boards at
http://www.planetee.com/forums/.

And look for a special report on ASIC handoff and methodology
trends in an upcoming issue of Elecronic Design Magazine.

Write me at: dmaliniak@penton.com

*******
2. News
*******
Agilent Updates Its RF Design Suite
The latest version of Agilent's ADS 2002C design tools for RF,
microwave and wireless communication products brings upgrades in
simulation technology and usability for RF system, circuit and
physical design. Advances in the software over the previous
release include a multi-threaded Agilent Ptolemy simulation, a
TD-SCDMA Design Library and a link to Agilent's ESG Signal Studio
software.

Agilent ADS 2002C is equipped with a new feature that adds
circuit and physical co-optimization to co-simulation with layout
components introduced earlier this year. The new feature allows
ADS to adjust both circuit component values and layout dimensions
to optimize physical and circuit performance. The co-optimization
with layout components feature uses ADS' EM simulator, Momentum,
and features including RF mode for fast analysis of electrically
small circuits and arbitrary polygonal mesh for high levels of
accuracy and speed. The suite is available now. Prices start at
$8,400.
http://eesof.tm.agilent.com/

*******
3. News
*******
Accellera Elects New Officers
Accellera, the electronics industry organization focused on
language-based design standards, today announced that its Board
members(systems, semiconductor and design tool companies) have
elected a new slate of officers. Dennis Brophy, director of
strategic business development at Model Technology, was elected
Accellera's chair for a third term. Shrenik Mehta, senior
engineering manager, Sun Microsystems, was elected vice chair.
Steve Wang, vice president and co-founder, Axis Systems, was
elected treasurer. Karen Bartleson, director of quality and
interoperability, Synopsys, was re-elected secretary for a third
term.
http://www.accellera.org/


*******
4. News
*******
Coolsand Turns To Axis For High-Level Verification
Coolsand Technologies Inc., Paris, France, has chosen Axis
Technology's Xtreme verification system and is using it early in
the design flow to verify the architecture of a system-on-a-chip
(SoC) for the portable multimedia consumer electronics market.

Coolsand's multimedia chip is a complex, highly integrated SoC.
The main reason Coolsand needed Xtreme so early in the flow was
to run the millions of simulation cycles needed to verify the
performance and interoperability of computation-intensive
multimedia functions mapped in hardware. Architectural
verification was accomplished very early, running C code on the
Axis system. Axis introduced its language-neutral verification
platform in March 2002. The newest versions of Axis' Xcite and
Xtreme verification systems support both VHDL and Verilog with no
restrictions between language boundaries. During simulation,
acceleration, and emulation, customers now can arbitrarily mix
both languages in the same design, and debug any signal within
that design -- whether it's a VHDL or Verilog signal.
http://www.axiscorp.com/

*******
5. News
*******
Tensilica Unveils New Instruction Set Architecture

In previewing the next generation of its Xtensa processor ISA
(instruction set architecture) at last week's Microprocessor
Forum, Tensilica Inc.'s chief architect, Bill Huffman, covered
ideas for a long instruction word format for designer-defined
instructions that has many of the benefits of VLIW (performance)
but none of the drawbacks (code bloat). Tensilica calls this
configurable architecture FLIX for Flexible Length Instruction
Xtensions.

The FLIX capabilities will allow designers to add custom TIE
(Tensilica Instruction Extension) language instructions that use
longer word lengths to achieve greater parallelism and higher
performance. FLIX will allow a modeless mix of 16-, 24-, and
64-bit instructions so code can be fast and parallel when needed
or compact when parallelism isn't needed. Using the TIE
language, designers can develop an
unlimited variety of designer-defined instructions for
applications ranging from communications processors to consumer
multimedia. The FLIX-enhanced ISA will be fully upwards
compatible with all current Xtensa processor configurations.
http://www.tensilica.com/

*************
6. Happenings
*************

IEEE International High Level Design Validation And Test Workshop
Côte d'Azur, Cannes, France
October 27-29, 2002
http://lists.planetee.com/cgi-bin3/flo?y=eN2s0DJhFR0BSK05Ar0Ai

IP-Based SOC Design Workshop
Espace Congres du World Trade Center, Grenoble, France
October 30-31, 2002
http://lists.planetee.com/cgi-bin3/flo?y=eN2s0DJhFR0BSK05cl0AC

IEEE International Conference on Computer-Aided Design (ICCAD)
Doubletree Hotel, San Jose, CA
November 10-14, 2002
http://lists.planetee.com/cgi-bin3/flo?y=eN2s0DJhFR0BSK05As0Aj

Conference on Design of Circuits and Integrated Systems (DCIS)
Palacio de la Magdalena, Sanstander, Spain
November 19-22, 2002
http://lists.planetee.com/cgi-bin3/flo?y=eN2s0DJhFR0BSK05cm0AD

DesignCon 2003
Santa Clara Convention Center, Santa Clara, CA
January 27-30, 2003
http://lists.planetee.com/cgi-bin3/flo?y=eN2s0DJhFR0BSK05cn0AE

Design and Verification Conference and Exhibition (DVCon,
formerly HDLCon)
Doubletree Hotel, San Jose, CA
February 24-26, 2003
http://lists.planetee.com/cgi-bin3/flo?y=eN2s0DJhFR0BSK05co0AF

EDA ALERT e-NEWSLETTER CONTACTS

===============================

EDA Technology Editor, Electronic Design: David Maliniak
mailto:dmaliniak@penton.com

Advertising/Sponsorship Opportunities:
Bill Baumann, bbaumann@penton.com

=========================

To subscribe send a blank email to:
mailto:EDA_Alert_Sub@lists.planetee.com
To unsubscribe send a blank email to:
mailto:EDA_Alert_Unsub@lists.planetee.com
Penton's e-Newsletter homepage:
http://lists.planetee.com/cgi-bin3/flo?y=eNOj0DJhFR0C4C0Jvu0Ah

===============================
Copyright 2002 Penton Media Inc.