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| EDA Alert e-Newsletter |
March 18, 2008
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ESC
Silicon Valley: Learn Today, Design Tomorrow
ESC Silicon Valley is where the global design engineering community
gathers to learn, collaborate and celebrate innovation. ESC is
celebrating 20 years of educating the creators of technology at the San
Jose Convention Center from April 14 - 17 with over 350 exhibiting
companies and over 200 new courses to this year's conference. Register today! Use Code: UX2-D
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Verify SoCs Faster And More Predictably With
SystemVerilog And Constrained-Random Stimuli
By Henry Angulo, Praveen Devulapalli, et al.
Synopsys Inc.
and Texas Instruments
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Verifying the integration and operation of new IP in a legacy
system-on-a-chip (SoC) becomes challenging. This is true particularly
when the legacy SoC environment was built using a directed test
methodology and validation of new IP requires corner case stimulus to
achieve required functional coverage.
Read the
full article...
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Our editors have been busy! Come read their commentaries and check
out exclusive videos from the Mobile World Congress, APEC, and Embedded World exhibitions and see the technology of
tomorrow from major players in the electronics industry.
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An Update On SystemC And TLMs
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Having found its niche as a verification vehicle, the SystemC
language and ecosystem continues to evolve under the aegis of the Open
SystemC Initiative (OSCI), a confederation of organizations with various
degrees and styles of interest in the language. I recently had occasion
to chat with Mike Meredith of Forte Design Systems, who serves as
OSCI’s president, and to catch up on some of the activities in the
various OSCI working groups.
Read the
full article...
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Router Boosts Analog Routing Productivity For
Matched Devices
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Laying out matching devices in custom analog circuits is an
error-prone, time-consuming job that can kill analog design yield. Such
devices can comprise up to 40% of the devices in a circuit. Silicon
Canvas’ matching device router, Laker-MDR, facilitates the special
routing requirements of analog-matching devices and automatically
generates electrically equivalent routes free of design-rule errors.
Read the
full article...
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Engine Tinkering Boosts HSpice’s
Horsepower
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Improvements to the core engine technology behind Synopsys’s
HSpice simulator, combined with multi-threading capabilities, gives the
tool new life in terms of performance for complex analog and
mixed-signal designs. As a result, circuit designers can now run HSpice
post-layout simulations up to three-times faster on single-core
processors and up to six-times faster on four-core processors than
previous versions.
Read the
full article...
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Flow Analyzes Process Variability
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IMEC has developed a variability-aware modeling (VAM) flow that
analyzes process variability of technologies below 45 nm. This flow
enables designers to optimize their system design for timing, energy,
and yield versus expected application load.
Read the
full article...
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In our March 27 cover story,
Technology Editor Daniel Harris will look at the state of robotics
technology. Which development will we need to see the most before we get
a robot in every home?
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- Less expensive sensors
- Better development software
- Smarter artificial intelligence
- More engineers to design the technology
- Government support
To take the poll, click here. Remember to scroll down, the poll is at
the bottom of the page.
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Free Whitepaper From Cadence
Build 45-nm chips that meet your desired performance goals using
"signoff in the loop" technology. By using a single signoff engine, you
can significantly improve predictability, productivity, and performance.
Download this free whitepaper to find out how this solution can help
designers and verification engineers.
Register Now
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Webinar: Improving The Accuracy Of Eye
Pattern Measurements
Presented by LeCroy
April 9 at 2 pm
ET
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While eye patterns are a commonly used for signal-integrity
analysis, they provide limited usable information about signal
integrity. Without very large numbers of measurement samples, testing
against compliance masks can lead to ambiguous results. Furthermore,
common measurements of signal parameters such as eye height are of
limited value at high signal rates due to the complex statistics of the
signal amplitude.
This Web seminar, presented by LeCroy Business Development Manager,
Michael Schnecker, will describe the limitations of eye-pattern testing
and some of the more important eye-based measurements. A measurement
technique using the normalized q-scale method from jitter analysis and
expanded to two dimensions will be described and its application to mask
testing and signal measurements will be demonstrated.
If you work on high bit-rate serial-data signals above approximately 3
Gb/s or are interested in signal integrity measurement, this free
seminar is for you.
Click here to register
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WIRELESS SENSING NETWORKS- A Survey of Design Options
Developing a wireless sensor network can be an awesome challenge or a
simple matter of picking the right module, depending on who you ask.
Off-the-shelf solutions have certain advantages, but may not be the best
overall solution to your problem. Home grown or custom solutions can be
designed to overcome specific challenges, so they can be critical for
certain projects. Learn more about the technical pros & cons of both
options in this live course set for April 30th at 2pm eastern.
Register now!
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CMOS Circuit Design, Layout, and Simulation:
Second Edition
By R. Jacob Baker
ISBN: 978-0-470-22941-5
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So for those who are up-and-coming hotshot designers, as well as the
veterans who’ve seen a lot of scaling in their time, there’s a good
deal of meat in this 1000+ page reference. Covering both long- and
short-channel CMOS technologies in a two-path approach, the book begins
with the basics, including an introduction to Spice simulation. After
chapters on the makeup of a CMOS device, it moves into operational
aspects as well as CMOS fabrication.
Read the
full article...
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