SystemVerilog is the natural evolution of the Verilog language, extending its capabilities for both design and verification. Demand for this advanced language is clear. Over a dozen EDA companies announced plans for product support of SystemVerilog in 2004; some support System-Verilog today.
To develop SystemVerilog, Accellera (www.accellera.org) assembled over 120 experts. Operating under the constraint of compliance with the Verilog language, they took a strong technology foundation and melded it into a language that addresses all levels of design abstraction, from transistors to systems. SystemVerilog's evolution occurred in several facets.
Language experts developed the architecture and semantics to ensure interoperability (see the figure). System-Verilog's components include:
- Design: because of its focus on RTL and behavioral synthesis, System-Verilog raises the level of design descriptions to transaction-based.
- Testbench: it accelerates software and hardware.
- Assertions: they can be simulated and formally verified.
- Direct Procedural Interface: makes for easier integration of C/C++ models.
The language's design centers on an object-oriented methodology, allowing a natural approach for intellectual property (IP) reuse. The interface section adds protocol interfaces that can be connected to any component for system design. Models of different types can be mixed. Also, there are mathematically based semantics, which are fundamental for assertions. Overall, each language addition has a simulation, formal, and synthesis semantic.
To facilitate design for verification, assertions add design intent for assertion-based synthesis and verification, and system-level verification. Interface enhancements raise the level of design and verification with formal- and simulation-based aspects to improve design quality and speed up verification.
Looking forward, Accellera plans to unify its Property Specification Language (PSL) with SystemVerilog 3.1 assertions to produce PSL 1.1 and synchronize Accellera's Verilog analog/mixed-signal (Verilog-AMS) standard with System-Verilog syntax. Accellera will assign the copyright of SystemVerilog 3.1a to the IEEE for standardization consideration before the 41st Design Automation Conference.
Mixing standardization with timely feedback yields many new functions and abilities in SystemVerilog, revolutionizing how systems are designed and verified. Designers and EDA vendors can leverage SystemVerilog now and in the future.
SystemVerilog is the natural evolution of the Verilog language, extending its capabilities for both design and verification. Demand for this advanced language is clear. Over a dozen EDA companies announced plans for product support of SystemVerilog in 2004; some support System-Verilog today.
To develop SystemVerilog, Accellera (www.accellera.org) assembled over 120 experts. Operating under the constraint of compliance with the Verilog language, they took a strong technology foundation and melded it into a language that addresses all levels of design abstraction, from transistors to systems. SystemVerilog's evolution occurred in several facets.
Language experts developed the architecture and semantics to ensure interoperability (see the figure). System-Verilog's components include:
- Design: because of its focus on RTL and behavioral synthesis, System-Verilog raises the level of design descriptions to transaction-based.
- Testbench: it accelerates software and hardware.
- Assertions: they can be simulated and formally verified.
- Direct Procedural Interface: makes for easier integration of C/C++ models.
The language's design centers on an object-oriented methodology, allowing a natural approach for intellectual property (IP) reuse. The interface section adds protocol interfaces that can be connected to any component for system design. Models of different types can be mixed. Also, there are mathematically based semantics, which are fundamental for assertions. Overall, each language addition has a simulation, formal, and synthesis semantic.
To facilitate design for verification, assertions add design intent for assertion-based synthesis and verification, and system-level verification. Interface enhancements raise the level of design and verification with formal- and simulation-based aspects to improve design quality and speed up verification.
Looking forward, Accellera plans to unify its Property Specification Language (PSL) with SystemVerilog 3.1 assertions to produce PSL 1.1 and synchronize Accellera's Verilog analog/mixed-signal (Verilog-AMS) standard with System-Verilog syntax. Accellera will assign the copyright of SystemVerilog 3.1a to the IEEE for standardization consideration before the 41st Design Automation Conference.
Mixing standardization with timely feedback yields many new functions and abilities in SystemVerilog, revolutionizing how systems are designed and verified. Designers and EDA vendors can leverage SystemVerilog now and in the future.