The two groups came together to ensure the OCP-IP TLMs can be built in the future on top of the standard OSCI APIs. By teaming up, the groups hope to eliminate any possibility of competing standards. OSCI plans to provide generic TLM transport functionality, while OCP-IP foresees using that functionality to implement models of its specific communication channels.
POWERING UP* Power predominates the thoughts of many designers as they contemplate the shift to subnanometer process technologies. There's good reason for this: Technology scaling and resulting soaring gate counts carry serious implications in terms of power. There will be increased leakage and dynamic power, as well as decreased chip reliability due to voltage-drop and electromigration effects.
If a problem is on the mind of designers, you can bet it's on the mind of EDA vendors. Synopsys' Galaxy Power epitomizes some of the industry offerings for optimizing power in 90-nm IC designs. It delivers up to a 2× leakage-power reduction without impacting the implementation flow. On top of that, it offers new capabilities for standby-mode (state-retention) designs and support for multithreshold designs.
For low power, Galaxy Power performs power-grid synthesis and power optimization with support for automatic hierarchical clock gating, multivoltage designs, multithreshold leakage, and state-retention power gating. Vector-free power analysis and sign-off-level power integrity are also part of the package.
Magma Design Automation also integrated power optimization and management into its RTL-to-GDSII flow. Blast Power is a forthcoming option to Magma's Blast Create and Blast Fusion APX methodology, which includes embedded power, timing, and rail analysis as well as power-minimization techniques. With Blast Power, Magma users can create power-vs.-timing and power-vs.-area tradeoffs throughout the flow without exporting design data outside of the Magma system.
Blast Power provides power-aware synthesis, automatic power-grid synthesis, and leakage-power optimization using multiple-threshold voltage libraries. Like Galaxy Power, it supports designs via multiple voltage domains and provides for power-aware placement and optimization.
Determining the severity of power-integrity issues is, in itself, vexing. Sigrity's XcitePI tool performs dynamic simulation of the full-chip power-grid structure, with package effects, to get a handle on the extent of power problems (Fig. 2).
Typically, a power grid's resistive, capacitive, and limited inductive coupling effects are dealt with using lumped off-chip RLC models. XcitePI instead analyzes the power grid with distributed electromagnetic-field propagation effects of the package. It also considers the capacitive and inductive coupling between all conductors in the chip's power grid.
Often, noise propagates to other areas of a chip through the package power and ground structures, rather than the power grid. Lumped off-chip RLC models can't readily model such effects. XcitePI performs transient analysis of the IC power grid while dynamically simulating electromagnetic fields in the package power and ground planes.
Power issues are also a concern for silicon foundries. Taiwan Semiconductor Manufacturing Co. (TSMC) has rolled out its Reference Flow 5.0. It's viewed as the industry's first reference flow providing critical power closure and integrated chip-to-package design for nanometer SoCs. The flow is built around tools such as Cadence Design Systems' Encounter digital-IC design platform and Synopsys' Galaxy design platform. It includes specialty tools from Mentor, Apache Design Solutions, Atrenta, and Optimal.
Reference Flow 5.0 addresses dynamic power optimization, leakage power optimization, and static and dynamic IR-drop final verification. When implementing SoCs in TSMC's Nexsys 90-nm technology, users will be able to insert level-shift cells and isolation cells. Thus, blocks of circuits can run at different voltages, and circuit leakage between power domains is prevented.
On the power-integrity side, TSMC chose Apache's Redhawk-SDL power verification suite, which incorporates the effects of simultaneous switching (core, memory, and I/O), intrinsic and intentional decoupling capacitors, and on-chip and package inductive effects. Static-only approaches largely neglect all of these.
Atrenta's SpyGlass LP (for low power) made it into the TSMC flow for its ability to enforce good low-power design practices at RTL. It addresses architectural-level, low-power design techniques such as the use of voltage and power domains that have maximum impact on power consumption. Its set of techniques for use early in the SoC design cycle ensures automatic checking and generation of interface logic.
TSMC's chip-to-package integration flow also uses Atrenta's SpyGlass ERC. It validates a gate-level netlist for a wide range of electrical rules and reports critical rule violations. SpyGlass ERC takes in Synopsys Liberty format (.lib) files along with a netlist to seek out problems like overloaded drivers, undesired clock interactions, delay-time dependent circuits, and library-specific errors. The idea is to achieve a clean netlist handoff to the physical implementation phase of the process.
Also key to TSMC's power-closure plans for 90-nm designs are several tools from Optimal Corp. The company's PowerGrid-DC addresses IR drop, current density, and Spice netlists. The PakSi-E and SIDEA tools extract package parasitics and generate timing data in Standard Delay Format (SDF).
In the past, the current entering an IC was relatively low, so the resistance created by the package (IR drop) was easily modeled and accounted for through package and lead selection. But in today's design environment, currents are very high and package IR drops can be stiff enough to cause havoc in a 1-V design. Thus, designers must ensure that power distribution is sufficient.
The methodology used in TSMC's Reference Flow 5.0 for power closure uses Optimal's PowerGrid-DC to create an equivalent resistive Spice netlist among the solder bumps (or bond wires) and solder balls (Fig. 3). The netlist is imported as a loading condition into third-party tools to perform IR-drop analysis. Then the interaction between chip and package is accounted for automatically.
Due to space constraints, signal traces in packages tend to have multiple lengths. Such differences must be compensated for on pc boards. Therefore, an automated flow is needed to quantify the timing delay from the I/O circuitry to the package pins for proper trace compensation on the board.