In the SNAP scheme, master AHB layers can connect up to eight cores per layer with improved arbitration. Further, AHB/APB slave branches can connect up to 16 slave cores per branch. The result is an interconnect matrix backbone that lets designers build topologies based on performance needs. For example, CPUs and memories can connect to high-speed paths with zero latency while slower peripherals can connect to peripheral branches, allowing optimization of gate counts.
A set of development tools that let designers quickly capture bus designs ties the SNAP solution together. The environment lets you evaluate key details about your proposed bus architecture in advance, including gate count, power dissipation, and speeds. The GUI enables users to enter information on the cores being connected and various interconnect parameters. The tool automatically generates the RTL for the interconnects themselves.
SPEEDING UP SPICE
On the full-custom design side, many designers have turned to fast-Spice derivatives for analog/mixed-signal simulation. Sure, they trade off a little accuracy, but they gain a great deal of speed. You can make up for the accuracy by simulating critical paths in a traditional Spice simulator in parallel. Meanwhile, for the bulk of your design, fast-Spice simulation gives you a big boost in verification speed.
Meanwhile, fast-Spice simulators keep improving in accuracy while still offering most, if not all, of the speed advantages. To wit, Berkeley Design Automation Inc. rolled out the 2009_05 release of its Analog FastSPICE (AFS) unified circuit verification platform.
Within a single executable, the AFS platform enables analog, mixed-signal, and RF design teams to verify what would otherwise require numerous simulators. Berkeley claims that this release delivers foundry-certified, true Spice accuracy with runtimes that are five to 20 times faster than traditional Spice for every type of analysis on circuits with up to 10 million elements. The result is twice the efficiency of traditional Spice simulators.
The platform includes new matrix solvers that deliver efficient convergence and fast transient analysis for pre- and post-layout circuits. In addition, the platform’s multicore capability provides up to two times more performance than singlethreaded analog fast-Spice simulators when run on up to four cores. An enhanced Monte Carlo analysis engine supports all commonly used features, including Latin hypercube sampling, in the industry’s most popular netlist styles.
GETTING IT RIGHT
There’s still significant room for innovation in the physical verification of large SoC designs, and such innovation ultimately translates into a competitive advantage for designers. It would be wonderful if physical verification runs didn’t take so long, but design teams will have to live with that downside of the process. Multicore tool architectures are chipping away at the runtimes. Still, if physical verification runtimes have to be so long, it would be nice if the runs could at least be more accurate.
That’s where Silicon Frontline Technology comes in. The startup launched its flagship tools for post-layout verification: F3D (Fast 3D) for fast 3D extraction and R3D (Resistive 3D) for 3D extraction and analysis of large resistive structures like power devices. These tools, which incorporate 3D technology, deliver guaranteed accuracy for full-chip, post-layout verification, according to Silicon Frontline. Fitting into standard design flows, the tools facilitate simpler adoption and quicker closure of the post-layout verification loop, the company says.
Silicon Frontline’s 3D parasitic-extraction technology lets users specify the level of accuracy desired, net by net, at block level or with regular expressions. The tools use an advanced field solver that eliminates the performance and capacity issues inherent in older field-solver technology, accomplishing full-chip extraction with greater accuracy, the company claims.
In Silicon Frontline’s benchmarks, F3D completed extraction of a 65-nm SoC design in under 10 hours. Extraction runs for metal-onmetal capacitors take less than three minutes versus over seven hours with standard field solvers. When performing extraction on a 40-nm design, F3D delivers accuracy that’s within 2% of silicon, Silicon Frontline says.
Pre-qualified by major foundries for accuracy, performance, and capacity, F3D suits sensitive analog and AMS circuits where coupling is a challenge—analog-to-digital converters, digitalto- analog converters, circuits with differential signals, MIM/MOMCaps (metal-insulator-metal/ metal-oxide-metal) and 3D devices, image sensors, and RF and high-speed designs—and for circuits manufactured at advanced technology nodes (65, 40, and 32 nm). R3D target applications include discrete or embedded power devices, where efficiency and reliability are important, as well as designs requiring analysis of large metal interconnects.