RF designers can look forward to tools that help eliminate off-chip passives and their performance-draining characteristics. Expect more tools for designing inductors, transformers, and filters into the ICs. Technologies as advanced as building acoustic resonators in silicon substrates to produce very high-Q filters are afoot, but again, toolsets for such design are lacking.
Expect to see more tools that address inductance extraction, which is increasingly an issue in achieving timing closure at clock rates of 500 MHz and higher. The embedding of RLC extraction within the place-and-route portion of the physical design flow will help, as will modeling of full-wave and mutual-inductance effects.
With clock rates spiraling past 2 GHz, 0.1-mm processes kicking in, and current drain increasing, power consumption is displacing timing closure as Public Enemy #1 in SoC design. Look for logic design tools that yield better understanding of power optimization and control. At the architectural level, designers need tools that can point the way to inherent power management that shuts down idle circuitry.
System-level design languages, C/C++ and Superlog among them, will advance in standardization, aiding in their widespread adoption. The recent approval of the Verilog-2001 standard (IEEE 1364-2001) is a step in this direction. It remains to be seen whether designers will move toward the top-down approach of object-oriented languages like C/C++, or the tried-and-true, bottom-up approach of behavioral Verilog extensions.
Silicon virtual prototyping will gain in prominence as a technology that fills the void between synthesis and place-and-route, feeding much-needed physical information back into the synthesis process. Virtual prototyping, which in the case of some tools is done on a full-chip level, can at least give the designer a platform from which to make decisions on block-level implementation. We can expect to see this technique gain in prominence in 2002.
At gigahertz clock rates, almost every element of a pc-board design is an effective RF radiator, leading to significant signal-integrity issues. Watch for pc-board tools that take more of a system approach to interconnect design. Users will see tools that integrate modeling and verification of the chip, package, and board environment for high-speed links.
FPGAs are climbing toward 50 million system gates by 2004. But the industry downturn has resulted in smaller design teams requiring tools that emphasize efficiency. Designers can look for FPGA design tools that offer advances in productivity and automation.
The 39th Design Automation Conference (June 10-14, 2002, New Orleans) will be, as always, the EDA industry's premier technical forum. It also is the showplace for the year's hottest new tools.
Functional verification remains a bottleneck as designers continue searching for the long-sought "intelligent testbench." Look for advances in automatic vector generation. Formal processes are emerging to tightly couple hardware/software design and verification flows with the original system specification.
2002 could see advances in tool interoperability between vendors, thanks to initiatives such as OpenAccess. Next year could be make-or-break for this effort. Version 2 of the OpenAccess API specification should appear by June's Design Automation Conference.
See associated timeline.