Analysis Tools: As part of its NanoCool low-voltage design initiative, Sequence Design will offer enhancements to two tools at DAC. PowerTheatre, which performs power analysis at the architectural level as well as RTL power optimization, now includes vectorless power analysis and SoC power modeling. The former enables upfront power analysis at the chip level without modeling, while designers can employ the latter to create detailed power models for IP blocks. One-year licensing costs $80,000.
Sequence's PhysicalStudio, for concurrent optimization of chip timing and signal integrity, now offers the ability to control threshold voltage at individual transistors to account for power leakage. The next release will also include analysis and optimization of electromigration and hot-electron effects in standard cell-based design. One-year licensing goes for $175,000.
Real Intent is announcing the addition of an assertion-based clock domain analysis capability to Verix. This feature offers analysis and formal verification of asynchronous interfaces in designs, as well as formal analysis for reliable clocking of synchronous designs.
On the RTL analysis front, Atrenta's SpyGlass SoC addresses the logical issues that designers confront when integrating IP from various sources. The tool creates a logical virtual prototype to help predict and eliminate problems in the HDL code. It performs both coding and structural analysis during the RTL design phase to address key SoC integration issues including clocking, verification, reuse, emulation, and testability. Prices start at $60,000 per year.
Another RTL analysis tool that looks ahead to implementation will be InTime Software's Time Planner. Billed as a design planning system, the product generates a physical floorplan directly from RTL, maintaining logical hierarchy and generating synthesis constraints to expedite runs. Prices start at $98,000 for time-based licenses.
Embedded memory is a subject of growing interest to SoC designers. SynTest is launching its TurboDebug-SoC/Memory tool, which gives users a means of debugging BISTed memory blocks ahead of production by diagnosing and locating memory faults in a pc-board prototype. Using the 1149.1 JTAG interface for communication between the PC and the chip under test, the tool annotates debug results on design schematics.
Pc-Board Tools: Cadence is showing the latest release of its pc-board design tools, with enhancements to both its Studio and Expert series flows. Of particular interest is the ability to measure differential signaling for die-to-die interconnect across both IC packages and pc boards (Fig. 2). Now incorporated in the SPECCTRAQuest design and analysis package, this technology allows users to simulate differential signals as a unit in pre- and post-layout simulations. A one-year license runs $24,200 and up.
A complete front-to-back, high-speed pc-board design system will be announced by Innoveda. The package, called Innoveda HSD, will cover all phases of pc-board design from definition to physical design to verification. Two specialized tool suites, DxDesigner HSD and PowerPCB HSD, target electrical engineers and pc-board designers, respectively. Pricing will be in the $100,000 range with availability arriving this summer.
Physical IC Design: New and tighter design rules demand a lot of IC routers. Plato Design Systems will show its NanoRoute-SI router for high-end SoCs at 0.13 µm and below. The tool performs routing and physical optimization concurrently, giving users a fast road to timing closure. It relies on Plato's graph-based routing engine, which eschews wireload models in favor of real physical optimization.
Cadence is unveiling broad upgrades to its synthesis/place-and-route flow at DAC. Changes include enhancements to BuildGates synthesis, Physically Knowledgeable Synthesis (PKS), and the Silicon Ensemble and SOC Encounter place-and-route systems. PKS will offer tight timing correlation and high capacity for rapid timing closure. Plus, a next-generation tool provides flexibility and productivity in power planning and routing. An embedded signal-integrity tool set grants crosstalk analysis and timing-driven post-route repair.
As process technology moves farther ahead, foundries release new design rules that see numerous minor tweaks. This produces a gap between the capabilities of designers' physical layout tools and the latest set of rules. Sagantec's SiFix tool automatically corrects and optimizes physical IC designs, relieving designers from design-rule complexity and the implementation of preferred rules (Fig. 3).
Design Languages: Look for a number of announcements at DAC related to high-level design languages, including Co-Design Automation's Superlog and SystemVerilog. Accellera is expected to announce the release of its awaited SystemVerilog standard just before the show kicks off. We should see some related vendor announcements regarding products.