Without a great deal of fanfare, electronic system- level (ESL) design tools have made their way into mainstream design methodologies. Consider high-level synthesis (HLS), or the notion of synthesizing a design into register transfer level (RTL) from a higher level of abstraction.
Launched in 2004, Mentor Graphics’ Catapult C has seen continual improvement. Mentor has now fully endowed Catapult C with the ability to synthesize control-logic blocks, enabling it to synthesize full chips from ANSI C++ to RTL. It’s also one of the best EDA releases of 2009.
It’s worth pointing out that in Mentor’s view, there are three different flavors of control logic. One is intrablock control logic, which typically isn’t explicitly coded in the C++ source but can be inferred. Catapult C has been able to synthesize this sort of intra-block control logic since its launch in 2004. In 2006, Catapult C introduced support for a second variety of control logic, known as multi-block dataflow control logic. The idea here is chaining single blocks to create a higher-level subsystem. Again, the control logic is not necessarily modeled in the source code but is inferred.
NEW ABILITIES
The leap forward in the latest incarnation of Catapult C is its ability to handle a third variety of control logic: synchronous, reactive inter-block control logic. Catapult C now can synthesize control-centric blocks that are purely reactive. With this kind of control logic, which is explicitly defined in the C++ source, it’s important to give designers a way to explicitly model the control logic. Users can now model a series of ports and make a decision when there’s a conflict.
In adding synthesis of this sort of reactive inter-block control logic, the challenge for Mentor was to determine how to maintain the abstraction benefits of C++ while permitting users to specify lower-level detail. The answer comes in the form of a new synthesizable C++ construct for asynchronous data communication.
The construct lets designers easily specify asynchronous data communication, allowing full control of the creation of concurrent hardware (Fig. 1). It also enables the interfacing of data-driven algorithms with control-centric blocks synchronized by clocks.
Getting these complex control-logic blocks from C++ to RTL is one thing, but making sure they still function properly at that level of abstraction is another. If a block exhibits unexpected behavior after synthesis to RTL, the challenge is figuring out why.
Mentor has filed for a patent on a technique for providing the necessary debug visibility into these kinds of of the RTL behavior onto the C++ source code. Designers can thus execute the C++ source code with the RTL behavior overlaid, enabling them to validate detailed RTL block interactions at the C level.
A final enhancement lies in power optimization. Many design teams have adopted clock gating as a power-management tool, but the insertion of clock gating is typically a manual, tedious process. Because Catapult C synthesizes the RTL from an untimed description, the tool can glean knowledge about the design through detailed sequential analysis. It uses the result of that analysis to automate the process of multilevel clock gating.
HOLD DOWN MEMORY POWER
Power optimization for the memory portions of systems-on-a-chip (SoCs) has lagged behind the logic circuitry. Although memory-IP (intellectual property) providers build complex power-management schemes into their products, it’s daunting for control-logic designers to take maximum advantage of them.
Seeing an opportunity to address this issue, Calypto Design Systems has brought its sequential analysis technology to bear on memory power optimization in the form of its PowerPro MG (memory gating) tool. PowerPro MG inserts sequential memory-gating logic into the design’s original register transfer-level (RTL) representation, which takes full advantage of the memory’s built-in power-optimization capabilities. This translates into significant reductions in both static and dynamic-memory power consumption.
In developing PowerPro MG, Calypto worked closely with Virage Logic to ensure that the tool would support Virage’s 40-nm SiWare memory compilers. The SiWare memories are highly configurable with options to control area, speed, power, and yield. From a power perspective, the memories offer multiple modes: a run mode, a standby mode (light sleep), a shutdown mode, and a dormant mode (deep sleep).
Driven primarily by array biasing, the memories’ light-sleep mode saves about 50% of static power. The shutdown and deep-sleep modes rely on integrated power switching. The deep-sleep mode turns off power to the memories’ periphery only, which saves some 70% of static power. Shutdown mode kills power to both the periphery and memory array itself, saving 90% of static power.
Where PowerPro MG makes its presence felt, though, is reducing dynamic power consumption. As shown by an example of a 1k by 32 Virage Logic 40-nm SiWare memory, the insertion of memory gating extends the amount of time during which the memory is inactive (Fig. 2). In a situation where the Memory Enable pin (ME) is low, or the memory is shut down, for 10% of the time, the bar chart shows total power consumption of about 7200 µW, about half of which is associated with dynamic power.
If PowerPro MG is used to insert memory gating, this ME-low time can be extended from 10% to 50% with a corresponding savings in dynamic power of about 43%. Adding more terms to the memory-gating functionality and extending ME-low time to 80% delivers dynamic power savings of 76%.
During ME analysis of the design, PowerPro MG can find situations where the ME pin can be shut down more frequently and for longer periods of time. That data is used to implement the light-sleep mode.