AnadigmDesigner offers over 50 such ready-to-use parameterizable analog functions. These include gain stages, summing amplifiers, sample-and-hold (S/H) amplifiers, high-, low-, and bandpass/stop filters, high- and low-Q filters, cosine filters, squarewave and sinewave oscillators, VCOs, full- and half-wave rectifiers, single- and dual-input comparators, dc reference voltages, limiters, peak detectors, Schmitt triggers, noninverting integrators, differentiators, and ramp and triangle waveform generators. Using this software, a designer can simply drag-and-drop necessary analog functional blocks and click a button to download the configuration onto the FPAA chip.
To allow engineers to evaluate the technology and develop working systems, Anadigm has released an evaluation board with a serial interface for PC connection. Analog circuits created with the CAD package can be easily downloaded onto the chip. The evaluation board additionally includes an 8-bit microcontroller, the HC08, which can dynamically modify the FPAA's functionality. "This feature permits the engineer to explore the concept of adapting analog performance in a software-controlled, event-driven environment," says Mike Kay, president of Anadigm.
Advanced Linear Devices (ALD) has leveraged its patented electrically programmable analog devices (EPAD) circuit-trimming technology to develop an ASIC design methodology for packing up to 50 op amps on a single CMOS die. Each op amp in this dense array can be electrically trimmed to better than 1.0 mV for high-precision applications. Initial efforts were focused on op amps. But according to John Skurla, ALD's marketing director, other functions like comparators, analog switches, and data converters can be implemented too.
For a sensor application, ALD has developed an eight-channel analog circuit using this methodology. Every channel comprises six EPAD-based op amps. Within it, each op amp serves as a building block. An on-chip multiplexer permits directing the injection or programming voltage to the right EPAD op amp. "While ALD's on-chip arrays are restricted to EPAD-based devices, the specifications can be tweaked to meet a designer's needs," Skurla asserts (see "Custom Linear Array Incorporates Up To 48 Precision Op Amps Per Chip," Electronic Design, March 19, p. 46).
Whereas some companies have demonstrated field-programmability and in-system reconfigurability in standalone analog ICs, others are bringing such programmability to system-on-a-chip (SoC) solutions. In a processor-centric SoC design, analog and I/O peripherals are normally fixed. Makers like Analog Devices, Texas Instruments, and Microchip Technology have added analog peripherals around their respective DSP/microprocessor cores to generate a complete system-level solution. But, these are primarily fixed.
As system needs continue changing rapidly with evolving standards, SoC solutions must also adapt quickly to changes in the chip's analog front end. Consequently, cost and time-to-market pressures demand new levels of flexibility and reconfigurability from SoC chips. This has motivated Cypress MicroSystems, a subsidiary of Cypress Semiconductor, to extend the proven programmable technologies of the digital world to the analog front. Combining programmable techniques with IPs and microcontroller architectures, Cypress MicroSystems has crafted a new generation of programmable SoC devices, known as PSoCs.
Toward this goal, Cypress MicroSystems has developed analog and digital building blocks called SoCblocs, which are integrated around a microcontroller core. These SoCblocs allow designers to realize analog and digital functions for a variety of embedded applications. Using multiplexers and switches, developers at Cypress MicroSystems have further interconnected these SoCblocs to create higher-level functions, labeled user modules. Subsequently, Cypress has generated a library of these modules, which include SAR ADCs, incremental ADCs, delta-sigma ADCs and DACs, programmable low-, high-, bandpass/stop filters, programmable-gain amplifiers, S/H amplifiers, waveform generators and detectors, and modulators/demodulators.
The initial launch consisted of about 40 analog and 30 digital user modules (see "Programmable SoC Delivers A New Level Of System Flexibility," Electronic Design, Nov. 20, 2000, p. 74). But the supplier intends to expand this library and enhance the resolution of the data converters. Right now, the converters in the library offer 12-bit resolution. Cypress plans to push that higher in next-generation PSoCs.
Employing the PSoC Designer, a Windows-based IDE software, a user can connect these higher-level user modules into a desired system. Using only a PC screen and icons, a user can configure and reconfigure both analog and digital arrays of the device graphically and then instantly map the system configured onto the PSoC chip by clicking an icon.
The PSoC Designer contains three subsystems; the device editor, an applications editor, and a debugger (Fig. 4). In the device editor mode, user modules are selected and interconnected, and then mapped onto the SoCblocs on-chip to realize the final PSoC microcontroller. The first PSoC family is built around the company's 8-bit M8C microcontroller core using the maker's proprietary silicon-oxide/nitride-oxide silicon (SONOS) programmable nonvolatile process, integrated with a high-volume CMOS SRAM process.
Field-programmable and in-system reconfigurable analog ICs have arrived. They will change analog design, making life easier for experienced and inexperienced designers alike.
AnadigmDesigner offers over 50 such ready-to-use parameterizable analog functions. These include gain stages, summing amplifiers, sample-and-hold (S/H) amplifiers, high-, low-, and bandpass/stop filters, high- and low-Q filters, cosine filters, squarewave and sinewave oscillators, VCOs, full- and half-wave rectifiers, single- and dual-input comparators, dc reference voltages, limiters, peak detectors, Schmitt triggers, noninverting integrators, differentiators, and ramp and triangle waveform generators. Using this software, a designer can simply drag-and-drop necessary analog functional blocks and click a button to download the configuration onto the FPAA chip.
To allow engineers to evaluate the technology and develop working systems, Anadigm has released an evaluation board with a serial interface for PC connection. Analog circuits created with the CAD package can be easily downloaded onto the chip. The evaluation board additionally includes an 8-bit microcontroller, the HC08, which can dynamically modify the FPAA's functionality. "This feature permits the engineer to explore the concept of adapting analog performance in a software-controlled, event-driven environment," says Mike Kay, president of Anadigm.
Advanced Linear Devices (ALD) has leveraged its patented electrically programmable analog devices (EPAD) circuit-trimming technology to develop an ASIC design methodology for packing up to 50 op amps on a single CMOS die. Each op amp in this dense array can be electrically trimmed to better than 1.0 mV for high-precision applications. Initial efforts were focused on op amps. But according to John Skurla, ALD's marketing director, other functions like comparators, analog switches, and data converters can be implemented too.
For a sensor application, ALD has developed an eight-channel analog circuit using this methodology. Every channel comprises six EPAD-based op amps. Within it, each op amp serves as a building block. An on-chip multiplexer permits directing the injection or programming voltage to the right EPAD op amp. "While ALD's on-chip arrays are restricted to EPAD-based devices, the specifications can be tweaked to meet a designer's needs," Skurla asserts (see "Custom Linear Array Incorporates Up To 48 Precision Op Amps Per Chip," Electronic Design, March 19, p. 46).
Whereas some companies have demonstrated field-programmability and in-system reconfigurability in standalone analog ICs, others are bringing such programmability to system-on-a-chip (SoC) solutions. In a processor-centric SoC design, analog and I/O peripherals are normally fixed. Makers like Analog Devices, Texas Instruments, and Microchip Technology have added analog peripherals around their respective DSP/microprocessor cores to generate a complete system-level solution. But, these are primarily fixed.
As system needs continue changing rapidly with evolving standards, SoC solutions must also adapt quickly to changes in the chip's analog front end. Consequently, cost and time-to-market pressures demand new levels of flexibility and reconfigurability from SoC chips. This has motivated Cypress MicroSystems, a subsidiary of Cypress Semiconductor, to extend the proven programmable technologies of the digital world to the analog front. Combining programmable techniques with IPs and microcontroller architectures, Cypress MicroSystems has crafted a new generation of programmable SoC devices, known as PSoCs.
Toward this goal, Cypress MicroSystems has developed analog and digital building blocks called SoCblocs, which are integrated around a microcontroller core. These SoCblocs allow designers to realize analog and digital functions for a variety of embedded applications. Using multiplexers and switches, developers at Cypress MicroSystems have further interconnected these SoCblocs to create higher-level functions, labeled user modules. Subsequently, Cypress has generated a library of these modules, which include SAR ADCs, incremental ADCs, delta-sigma ADCs and DACs, programmable low-, high-, bandpass/stop filters, programmable-gain amplifiers, S/H amplifiers, waveform generators and detectors, and modulators/demodulators.
The initial launch consisted of about 40 analog and 30 digital user modules (see "Programmable SoC Delivers A New Level Of System Flexibility," Electronic Design, Nov. 20, 2000, p. 74). But the supplier intends to expand this library and enhance the resolution of the data converters. Right now, the converters in the library offer 12-bit resolution. Cypress plans to push that higher in next-generation PSoCs.
Employing the PSoC Designer, a Windows-based IDE software, a user can connect these higher-level user modules into a desired system. Using only a PC screen and icons, a user can configure and reconfigure both analog and digital arrays of the device graphically and then instantly map the system configured onto the PSoC chip by clicking an icon.
The PSoC Designer contains three subsystems; the device editor, an applications editor, and a debugger (Fig. 4). In the device editor mode, user modules are selected and interconnected, and then mapped onto the SoCblocs on-chip to realize the final PSoC microcontroller. The first PSoC family is built around the company's 8-bit M8C microcontroller core using the maker's proprietary silicon-oxide/nitride-oxide silicon (SONOS) programmable nonvolatile process, integrated with a high-volume CMOS SRAM process.
Field-programmable and in-system reconfigurable analog ICs have arrived. They will change analog design, making life easier for experienced and inexperienced designers alike.