Once the design is created, it must be verified prior to the RTL to ensure that its functionality is as intended. At this point, the test bench should be created (Fig. 2). It will be used throughout the FPGA flow to verify the functionality of the design at the RTL level and the functional and timing gate levels.
A test bench is a separate set of VHDL or Verilog code that is connected to the design's inputs and outputs. Since these stay constant through synthesis and place and route, the test bench can be used at each stage to verify functionality.
The test bench has two purposes. It provides the stimulus and response information, such as clocks, reset, and input data, that the design will encounter when implemented in an FPGA device and installed into the final system. Also, it contains regression-checking constructs that allow key functionality to be tested throughout the FPGA HDL simulation flow.
The Cost Of The HDL Payoff
Test benches often contain the most complex HDL code in the design. An investment in learning VHDL or Verilog beyond just the basics will pay off greatly here. These intelligent test benches can be used to significantly enhance the designer's productivity in developing unit and system tests.
HDL-based design represents a new paradigm for some FPGA designers. The steps involved are straightforward, but like anything else that's worth doing, it requires going through a learning curve.
For example, FPGA designers must learn how to use an HDL compiler—a tool used to convert the HDL design into an executable representation. Most HDL compilers make this easy by providing defaults for compile options and easy-to-use graphical user interfaces. But if the HDL compiler or simulator produces error messages, the user must know how to determine what they have done wrong in the HDL design. Quality tools simplify this task by allowing the user to double click on the compiler message to link directly to the offending source code.
Designers also must learn to fully exploit the power of HDLs. Designing at a higher level of abstraction and then allowing the synthesis tool to produce an actual implementation requires faith in both the tools and the processes. The good news is that the HDL-based design process has already been well proven by literally thousands of designers.
As tool vendors have begun to address the unique requirements of FPGA designers, high-level design has finally come of age. Designers and engineering managers considering a switch to HDL-based FPGA design now have a variety of tools at their disposal from which to choose.
Selecting the appropriate tools is not a decision made on price considerations alone. Rather, designers must evaluate which tools are leaders in their class, offer upward mobility to higher levels of flexibility and functionality, and speed up the HDL learning curve.
Regardless of which tools you use, the bottom line is simple—advanced HDL design tools are a must for FPGA and ASIC designers alike.