DSP TAKING PRECEDENCE
"A huge trend in emerging FPGA applications has been in the DSP area," says John Gallagher, director of outbound marketing at Synplicity. Gallagher cites applications in military/aerospace systems, radar installations, satellites, and terrestrial radio.
The massive parallelization that's possible with FPGAs lends itself well to DSP applications, as well as other signal-processing scenarios. For instance, Xilinx has worked closely with the MathWorks to provide a plug-in for design with the latter's Simulink environment.
Xilinx's System Generator for DSP employs Xilinx's DSP function library and plugs those functional elements into either HDL or a bitstream for use in programming the functions into an FPGA. Xilinx's Accel DSP tool also figures into this flow. Accel DSP translates Matlab algorithms into HDL. Xilinx has been investigating ways to import the HDL that's generated by Accel DSP into System Generator for DSP.
Xilinx also teamed up with Synplicity to improve DSP resource utilization in Xilinx's Virtex FPGAs. Synplicity's Synplify DSP synthesis tool automates DSP implementation. It also provides for fast design-space exploration, thanks to its ties to the MathWorks' Simulink environment (Fig. 2).
Some interesting system implementations have been put in place using FPGAs for signal-processing applications. One, designed by the Center for Microelectronics at Aargau, Switzerland, involved a 32,768-point fast-Fourier transform (FFT) that pushes the limits of what can be implemented in a Virtex-2 Pro FPGA (see "An FPGA-Based Spectrometer For Solar Observation," Drill Deeper 13476).
DESIGN ANALYSIS
An ASIC-like flow for FPGA design demands ASIC-like design analysis, and both FPGA vendors and EDA vendors have stepped up to the plate in this respect.
On the power-analysis and optimization side, QuickLogic's QuickWorks suite of implementation tools includes what the company calls its PowerPlacer capability. Rather than perform place-and-route operations with only timing in mind, the PowerPlacer capability accounts for both timing and power.
QuickWorks also incorporates a power calculator, which presents worst-case power-consumption analysis and performs what-if analysis. On top of that, a power simulator takes in a netlist and shows which blocks in a design consume the most power. The results of the simulation can point the designer to problem areas in the circuit.
Actel's Libero integrated design environment, now in version 7.2, offers advanced power and timing analysis capabilities for users of its Fusion, ProASIC3, and RTAX-S logic families. Actel's SmartTime feature offers static timing-analysis capabilities based on standards such as the Synopsys design constraints, as well as visual constraint dialogues that help ease the transition from ASICs to mixed-signal FPGAs. Clock-source latency analysis, which allows the definition of a clock constraint for jitter, helps designers to analyze FPGA timing in the context of its surrounding environment.
Actel's SmartPower analysis tool was upgraded to generate power-consumption data for nets, gates, I/Os, RAM, FIFOs, and clocks. Or, it can generate data block-by-block by component type.
TAKING A SYSTEMIC VIEW
When contemplating any system integration, whether with ASICs or FPGAs, it's important to remember that the devices aren't designed and implemented and then thrown into a drawer. They must be developed with software in mind. Further, the designer must think in terms of the FPGA existing in residence on a pc board.
Altium's Designer suite of tools and associated development boards provide a single executable environment that handles FPGA design, board design, and full software development capabilities. The environment is fully interactive in that hardware and software are developed concurrently and with each domain having full awareness of the other.
"In our view of FPGA technology, we see it as a bridge between the hardware and software realms," says Rob Irwin, Altium's product marketing manager. "Our approach is to use the FPGA technology to unify the development of the hardware and software pieces of the puzzle."
On the chip-to-board side, the same kind of interactivity allows board design to be accomplished with full knowledge of the associated FPGA's pinout. If either the FPGA or board layout is changed, the other is changed to reflect it.
In a similar vein, Mentor Graphics' I/O Designer is intendedto close the gap between the FPGA and its interface to the pc board. I/O Designer aids the board-layout software in determining whether pins can be swapped. It also creates the pc-board symbols for the FPGA, which can be a time-consuming step.
DSP TAKING PRECEDENCE
"A huge trend in emerging FPGA applications has been in the DSP area," says John Gallagher, director of outbound marketing at Synplicity. Gallagher cites applications in military/aerospace systems, radar installations, satellites, and terrestrial radio.
The massive parallelization that's possible with FPGAs lends itself well to DSP applications, as well as other signal-processing scenarios. For instance, Xilinx has worked closely with the MathWorks to provide a plug-in for design with the latter's Simulink environment.
Xilinx's System Generator for DSP employs Xilinx's DSP function library and plugs those functional elements into either HDL or a bitstream for use in programming the functions into an FPGA. Xilinx's Accel DSP tool also figures into this flow. Accel DSP translates Matlab algorithms into HDL. Xilinx has been investigating ways to import the HDL that's generated by Accel DSP into System Generator for DSP.
Xilinx also teamed up with Synplicity to improve DSP resource utilization in Xilinx's Virtex FPGAs. Synplicity's Synplify DSP synthesis tool automates DSP implementation. It also provides for fast design-space exploration, thanks to its ties to the MathWorks' Simulink environment (Fig. 2).
Some interesting system implementations have been put in place using FPGAs for signal-processing applications. One, designed by the Center for Microelectronics at Aargau, Switzerland, involved a 32,768-point fast-Fourier transform (FFT) that pushes the limits of what can be implemented in a Virtex-2 Pro FPGA (see "An FPGA-Based Spectrometer For Solar Observation," Drill Deeper 13476).
DESIGN ANALYSIS
An ASIC-like flow for FPGA design demands ASIC-like design analysis, and both FPGA vendors and EDA vendors have stepped up to the plate in this respect.
On the power-analysis and optimization side, QuickLogic's QuickWorks suite of implementation tools includes what the company calls its PowerPlacer capability. Rather than perform place-and-route operations with only timing in mind, the PowerPlacer capability accounts for both timing and power.
QuickWorks also incorporates a power calculator, which presents worst-case power-consumption analysis and performs what-if analysis. On top of that, a power simulator takes in a netlist and shows which blocks in a design consume the most power. The results of the simulation can point the designer to problem areas in the circuit.
Actel's Libero integrated design environment, now in version 7.2, offers advanced power and timing analysis capabilities for users of its Fusion, ProASIC3, and RTAX-S logic families. Actel's SmartTime feature offers static timing-analysis capabilities based on standards such as the Synopsys design constraints, as well as visual constraint dialogues that help ease the transition from ASICs to mixed-signal FPGAs. Clock-source latency analysis, which allows the definition of a clock constraint for jitter, helps designers to analyze FPGA timing in the context of its surrounding environment.
Actel's SmartPower analysis tool was upgraded to generate power-consumption data for nets, gates, I/Os, RAM, FIFOs, and clocks. Or, it can generate data block-by-block by component type.
TAKING A SYSTEMIC VIEW
When contemplating any system integration, whether with ASICs or FPGAs, it's important to remember that the devices aren't designed and implemented and then thrown into a drawer. They must be developed with software in mind. Further, the designer must think in terms of the FPGA existing in residence on a pc board.
Altium's Designer suite of tools and associated development boards provide a single executable environment that handles FPGA design, board design, and full software development capabilities. The environment is fully interactive in that hardware and software are developed concurrently and with each domain having full awareness of the other.
"In our view of FPGA technology, we see it as a bridge between the hardware and software realms," says Rob Irwin, Altium's product marketing manager. "Our approach is to use the FPGA technology to unify the development of the hardware and software pieces of the puzzle."
On the chip-to-board side, the same kind of interactivity allows board design to be accomplished with full knowledge of the associated FPGA's pinout. If either the FPGA or board layout is changed, the other is changed to reflect it.
In a similar vein, Mentor Graphics' I/O Designer is intendedto close the gap between the FPGA and its interface to the pc board. I/O Designer aids the board-layout software in determining whether pins can be swapped. It also creates the pc-board symbols for the FPGA, which can be a time-consuming step.