Logic synthesis represented a much more optimal way to translate and transform an abstract description of a circuit to a gate-level schematic than previous methods. That profoundly impacted the design process, notes Cadence's Vucurevich. For some time by the late 1980s, there had been the notion of the "tall, skinny designer," or a designer who had the insight and skills to take a project from conception all the way through realization. The design methodology brought to fruition in the ASIC age of logic synthesis re-established the division of labor between the front and back ends of the design process.
But synthesis advocates saw in the methodology potential to join these realms again through behavioral synthesis. This approach would start from a level above RTL, which is to say a purely behavioral description of the system, and go all the way down to gates. The idea harks back to Carver Mead's concept of silicon compilers. These were worked on for a time in the mid-1980s but ultimately abandoned as a less efficient, and less broadly applicable, alternative to synthesis.
Broad acceptance of synthesis brought with it an expanded design automation industry in the form of a raft of "point tools," or tools for specific verification and analysis tasks throughout the design flow. Throughout the '90s, the synthesis-based front-end flows were refined and improved to keep up with Moore's Law.
Today's engineers are on the verge of yet another sea change in the EDA landscape. A hallmark of the design automation evolution has been that it began at the lowest possible levels of abstraction, or the physical domain. The masking process saw design automation first. "That's because the most complex parts are the closest to the mask, which is where you have the most objects," says Synopsys' Camposano. It was far easier to create a database of polygons and print them on a plotter than to draw them by hand.
Place and route fell next because it was the next level up in terms of the number of objects to be handled. Then, once standard-cell methodologies were developed, logical design was the next target.
If we follow the thread, behavioral methodologies are the next obvious stage in automation. A new level of abstraction, higher than RTL, will allow system-level designers to specify the function they want, then have a wide range of implementation options. One initiative to watch in this area is the Metropolis initiative of the Gigascale Silicon Research Center, which strives to create a metamodel for functionality based on abstract algebra that assumes no form of implementation.
Meanwhile, today's cell-based ASIC-style design methodologies push forward into the system-on-a-chip (SoC) age. The clean handoff between the domains of logical and physical design that has been the dominant paradigm of the ASIC age is no longer so clean in the era of SoCs and ultra-deep-submicron (UDSM) silicon fabrication. In fact, it's collapsing quickly as the dominance of interconnect in delay calculations grows. Front-end designers can no longer "throw their designs over the wall" to designers who specialize in physical implementation without knowledge of how their work is expressed in silicon.
Thus, a new era has begun in design tools that merges the logical and physical (see this issue's cover story, p. 45). Going forward, there will be much more emphasis on signal integrity and analysis of physical effects at UDSM geometries. All of these issues are ways in which EDA tools will aid designers in conquering the complexity that's to come as silicon fabrication continues to keep pace with Gordon Moore's Law, 37 years old but still holding true.