Gain Abstraction And Accuracy From RTL Power Estimation

Excessive power consumption can destroy a design’s commercial viability. Modern cell phones are permitted to consume no more than a few hundred milliwatts for voice communications. Yet in the past, designers were forced to estimate power consumption using a manual spreadsheet approach with inaccuracies of scores of milliwatts. Worse, the design of an advanced 3G phone with multiple functions—camera, video, audio, and data connectivity—will be especially power-critical. Measuring power consumption only after you’ve produced silicon prototypes, or even synthesized logic to gates, is far too late.

So how can you know early in the design cycle whether you’ve exceeded the power budget? How can you optimize the design for power early enough to avoid time-consuming, late-stage redesigns?

This article describes a register-transfer-level (RTL) power-estimation methodology that designers have shown to be accurate to within 8% to 15% of actual silicon power consumption. Such accuracy is more than sufficient to make the critical “big-picture” analyses and decisions that determine chip-level power consumption and to support an RTL power sign-off milestone.

But let’s first ask: “What’s wrong with traditional power-estimation methodologies?” The manual spreadsheet approach has broken down in the face of nanometer design complexity, exacerbated by the need for greater accuracy—especially for leakage power—at smaller process nodes and by interdependent power-management techniques. This has robbed design teams of the up-front analysis necessary to guide chip architecture decisions. Chip micro-architecture is a major determinant of chip power consumption—accounting for 80% or more of the power. Consequently, the failure of the spreadsheet approach presents quite a serious problem for chip architects.

Moreover, power analysis undertaken at the gate level has failed for the same reasons. Worse, the gate and transistor levels of abstraction are microscopic levels that possess no chip micro-architecture context. This severely limits the designer’s ability to identify power-hungry functional scenarios and devise appropriate “worst-case power” stimuli. In addition, these microscopic levels of abstraction overload not only the designer, but also the performance and capacity of power-estimation tools. In any case, gate-level power estimation is executed far too late in the design flow to take significant power-reduction measures.

Now we come to the question of economics and effort. Choosing power-estimation and power-reduction methodologies involves not only what they can (and cannot) do and how well they do it, but at what cost. Costs include power-estimation tools and model libraries (and their up-keep), the additional die area used to implement power-management techniques, and the cost (and time) to achieve the power-consumption objectives. These costs, of course, affect both the design team’s budget and the device’s economic competitiveness.

Certainly, designers have their favored power-management techniques (Fig. 1). These data were collected from 115 respondents to a targeted survey conducted by the authors. The respondents were SoC designers in wireless telecommunications (31%), portable electronics (21%), and networking (27%).

Clearly, these power-management techniques are in widespread use. Thus, the selected power-estimation methodology must measure the effects of these techniques in any given design with sufficient accuracy. The designer can therefore deploy them with maximum effectiveness. This then begs the question: What is that power-estimation methodology?

The Story At RTL
RTL is the level of abstraction that possesses both the micro-architectural context for determining “big-picture” power consumption and the structural detail necessary for reasonably accurate analysis. It’s the prime level at which the effects of power-reduction techniques, such as clock gating, power gating, mixed threshold voltages, voltage islands, and memory partitioning, can realistically be estimated. And it’s also the point in the design flow at which effective remedial action can be taken with minimal adverse effects on design time.

However, this raises a question: Is RTL power estimation accurate enough? User-reported silicon correlations can be shown for an RTL power-estimation methodology (such as Sequence Design’s PowerTheater) compared to those for the gate level, Spice, and silicon (Fig. 2), which assumes a simulation vector set common to all levels. Here, RTL estimation results correlate to within 8% to 15% of silicon, and even overlap gate-level estimation results. Indeed, a leading consumer electronics manufacturer has reported a correlation between RTL and gate level of within 3% to 8% on three designs.

The difference between RTL and gate-level results is determined largely by power model accuracy and the algorithms used by the RTL estimation methodology. Largely, the libraries and simulation vector factors determine the difference between the gate-level results and silicon.

This RTL correlation is sufficient to establish an RTL power sign-off milestone—similar to the functional/timing sign-off that’s been used for over two decades.

How it works
So, how does such an RTL power-estimation methodology work? We’ll start by defining what must be measured, and then derive and discuss some basic methodology attributes necessary for accurate measurement.

The total power consumption—the sum of dynamic and static power consumption factors—of a device is expressed as:

P_TOTAL = P_DYNAMIC + P_STATIC,

where P_DYNAMIC = (Pdyn_cells + Pdyn_loads) and

P_STATIC = (Pstatic_current + Pstatic_state)

It should be noted that static power consumption has increased—both in absolute terms and as a proportion of total power consumption—as processing technology has moved to ever-smaller feature sizes. Indeed, at 90 nm and 65 nm, static power consumption constitutes 20% to 30% of total power consumption (Fig. 3).