The 43rd DAC kicked off in traditional fashion late Sunday afternoon with the annual Gartner Dataquest reception and briefing. Held in the San Francisco Marriott, the Dataquest gathering is when we all know for sure that DAC has begun. The reception is a great opportunity to touch base with old friends, make a few new ones, and to gather a few data points to test over the course of DAC itself. But primarily, it’s a platform for Gartner’s semiconductor and design analysts to deliver their assessments of how the semiconductor and EDA industries are expected to fare, and of the trends they see emerging that’ll influence their predictions.
As always, the presentations begin with an introduction from the chairman of the Electronic Design Automation Consortium (EDAC). Wally Rhines of Mentor Graphics has passed the chairman’s baton to Synopsys’ Aart de Geus. de Geus, in his typical fashion, managed to mix a little humor into his otherwise straightforward rundown of EDAC’s spheres of influence. Suffice to say, we eventually learned just why de Geus insisted that Gartner’s chief EDA analyst, Gary Smith, wear a white suit for the occasion.
ASICs Heading Toward 32 nm
Batting leadoff for Gartner’s analyst team was Research VP Bryan Lewis, who covers ASICs, SoC, and FPGAs. Lewis introduced one of the subthemes that ran through many of the afternoon’s presentations: the notion of restrictive design rules (RDRs) becoming prevalent at the 32-nm process node, possibly by 2010. RDR, also known as structured regular silicon, is a concept that, according to Gary Smith, has already been proven at IBM at the 45-nm node. It centers on creating chips from wafers of pre-designed arrays of logic cells. According to Lewis, nodes below 45 nm may need a more rigid architecture if designers are to increase yield predictability. As would be pointed out later, the use of RDRs at 32 nm may have repercussions for the EDA industry.
In discussing platform-ASIC alternatives, Lewis noted that the concept of cell-based ASICs with a PLD partition has not yet taken off. Cell-based options, exemplified by Texas Instruments’ OMAP platform, are doing quite well.
Lewis confirmed what was already obvious regarding structured ASICs, namely, that they’re even more of a niche implementation option than Gartner had concluded in its 2005 forecast. LSI Logic abandoned the structured-ASIC market earlier this year. Hence, Lewis has halved his forecast for the structured-ASIC market, rolling his 2007 estimate back to $564 million (from $894 million) and his 2008 number to $700 million (from $1.4 billion). Yet, Lewis claims, structured ASICs are not dead.
Overall, ASIC design starts are down 6.4% for 2006. ASIC starts have leveled off from the precipitous declines of past years, but Lewis sees them continuing to decline at about the 5-6% rate for the next few years.
Lewis then shifted gears to talk about what he calls “second-generation SoCs,” and in so doing, he introduced yet another subtheme that ran through the presentations. In Gartner’s terminology, first-generation SoCs consist of a compute engine, memory, and associated logic subsystems. The emergence of multiple instances of that lineup on the same chip, with each compute engine possibly running a different operating system and a top software layer tying the chip together, constitutes a “second-generation” SoC. Philips’ Nexperia, TI’s OMAP, and Matsushita’s UniPhier devices are early examples of these multiprocessing SoCs.