First, Olsson stated that 450-mm wafer fabs will become a reality by 2014. The bad news, though, is that there will be only about 25 companies worldwide who will be able to afford the price tag of such a fab, pegged at $3.8 to $5 billion.
Nonetheless, says Olsson, almost all of the large integrated device manufacturers (IDMs) are investigating RDRs. Because of the inherently rigid architectures of RDR, widespread adoption of that technology will result in less costly, easier-to-use EDA tools.
It’s expected that some percentage of designs at 32 nm will use RDR. In Olsson’s view, if that percentage exceeds 40%, the result will be hampered growth in DFM tools. This pronouncement couldn’t have gone over too well with the DAC crowd, made up largely of EDA executives, many of whom have staked their futures on the growth of the DFM market.
Think Out Of The Box
As always, the Gartner presentations closed with Gary Smith’s talk. Smith tied together many of the threads that had emerged in the earlier presentations: RDR, software, and ESL. And, as usual, Smith challenged the assembled EDA luminaries to “think out of the box” to drive growth in their perennially stagnant industry.
Smith asked a pointed question: Is the EDA doing a good job? On the hardware side, sure. As he pointed out, the cost of designing an IC has held pretty steady ($10 million to $20 million) since 1997. The same can be said for verification. But why, then, is the cost of design overall rising so high? “It’s the software, stupid!” exclaimed Smith. As Daya Nadamuni had stated, more powerful hardware means more code. The software-development community has never been strong on efficiency. Yet, Smith maintains, programmability has replaced power as the key impediment to the continuing dominion of Moore’s Law.
How, then, is the EDA industry going to shake itself out of the doldrums that have pervaded it for so long? Well, it won’t be RTL tools, which have become a commodity as gate-level tools had by 1991. According to Smith, 5% growth in that arena is “optimistic.”
DFM-compatible tools drive growth in the IC CAD market. But Smith echoed Mary Ann Olsson’s comments in stating that if RDR takes hold by the 32-nm node, that growth would slow considerably.
One area that the EDA industry must look to for growth is the in-house-developed tools that are growing in prevalence at IDMs. Last year, Smith reported that such tools were used by 27% of design engineers. That figure has ballooned to 38%. The EDA industry needs to investigate which tools IDMs are building themselves and then figure out how to build them better for commercial sale. As an example, Smith mentioned Philips, which builds most of its own analog/RF tools in house as well as its ESL tools.
For many years now, Smith has held up ESL as a potential growth area for EDA. Calling 2006 “Year Two” of the ESL methodology in practical usage, Smith still sees ESL as a growth area but has focused on two “killer apps” for ESL. One, a concurrent software compiler, is a must-have for the success of Bryan Lewis’s 2G SoCs. Smith believes that the EDA industry has a better shot at developing a concurrent software compiler than does the embedded-system software developers. For one thing, EDA vendors have a much better understanding of concurrency. For another, compilation is a core competency for the EDA industry.
A second “killer ESL app” is what Smith terms the “architectural workbench.” As an example, think of The MathWorks and its architectural exploration tools and Matlab language. However, says Smith, the user of the architectural workbench isn’t a hardware or software engineer. It’s an electrical engineer. In Smith’s words, “develop this kind of tool for the engineers in Brazil or Bulgaria and it’ll be a winner.”
Smith concluded by exhorting the EDA industry to “take off its IC-design blinders.” The industry, he says, should develop tools for the entire design flow, with software design being a major roadblock.
First, Olsson stated that 450-mm wafer fabs will become a reality by 2014. The bad news, though, is that there will be only about 25 companies worldwide who will be able to afford the price tag of such a fab, pegged at $3.8 to $5 billion.
Nonetheless, says Olsson, almost all of the large integrated device manufacturers (IDMs) are investigating RDRs. Because of the inherently rigid architectures of RDR, widespread adoption of that technology will result in less costly, easier-to-use EDA tools.
It’s expected that some percentage of designs at 32 nm will use RDR. In Olsson’s view, if that percentage exceeds 40%, the result will be hampered growth in DFM tools. This pronouncement couldn’t have gone over too well with the DAC crowd, made up largely of EDA executives, many of whom have staked their futures on the growth of the DFM market.
Think Out Of The Box
As always, the Gartner presentations closed with Gary Smith’s talk. Smith tied together many of the threads that had emerged in the earlier presentations: RDR, software, and ESL. And, as usual, Smith challenged the assembled EDA luminaries to “think out of the box” to drive growth in their perennially stagnant industry.
Smith asked a pointed question: Is the EDA doing a good job? On the hardware side, sure. As he pointed out, the cost of designing an IC has held pretty steady ($10 million to $20 million) since 1997. The same can be said for verification. But why, then, is the cost of design overall rising so high? “It’s the software, stupid!” exclaimed Smith. As Daya Nadamuni had stated, more powerful hardware means more code. The software-development community has never been strong on efficiency. Yet, Smith maintains, programmability has replaced power as the key impediment to the continuing dominion of Moore’s Law.
How, then, is the EDA industry going to shake itself out of the doldrums that have pervaded it for so long? Well, it won’t be RTL tools, which have become a commodity as gate-level tools had by 1991. According to Smith, 5% growth in that arena is “optimistic.”
DFM-compatible tools drive growth in the IC CAD market. But Smith echoed Mary Ann Olsson’s comments in stating that if RDR takes hold by the 32-nm node, that growth would slow considerably.
One area that the EDA industry must look to for growth is the in-house-developed tools that are growing in prevalence at IDMs. Last year, Smith reported that such tools were used by 27% of design engineers. That figure has ballooned to 38%. The EDA industry needs to investigate which tools IDMs are building themselves and then figure out how to build them better for commercial sale. As an example, Smith mentioned Philips, which builds most of its own analog/RF tools in house as well as its ESL tools.
For many years now, Smith has held up ESL as a potential growth area for EDA. Calling 2006 “Year Two” of the ESL methodology in practical usage, Smith still sees ESL as a growth area but has focused on two “killer apps” for ESL. One, a concurrent software compiler, is a must-have for the success of Bryan Lewis’s 2G SoCs. Smith believes that the EDA industry has a better shot at developing a concurrent software compiler than does the embedded-system software developers. For one thing, EDA vendors have a much better understanding of concurrency. For another, compilation is a core competency for the EDA industry.
A second “killer ESL app” is what Smith terms the “architectural workbench.” As an example, think of The MathWorks and its architectural exploration tools and Matlab language. However, says Smith, the user of the architectural workbench isn’t a hardware or software engineer. It’s an electrical engineer. In Smith’s words, “develop this kind of tool for the engineers in Brazil or Bulgaria and it’ll be a winner.”
Smith concluded by exhorting the EDA industry to “take off its IC-design blinders.” The industry, he says, should develop tools for the entire design flow, with software design being a major roadblock.