POCA Coding: As mentioned previously, the HDL coding style for architectural synthesis is called pins-out-cycle-accurate, or POCA. This style can be written using any of the popular HDLs, including Verilog, VHDL, SystemVerilog, Superlog, SystemC, and CoWare C.
The basic premise of POCA is that the input and output transactions (reads and writes) of the module being created are explicitly fixed into clock cycle time, while all intervening calculations can be moved during optimization. As a result, the I/O protocol of the modules is the same before and after optimization. This overcomes a major headache found in behavioral synthesis where I/O protocols between modules are constantly shifting and made incompatible.
Language constructs used for POCA-style HDL coding are largely the same as those used in RTL-based design. While POCA permits more-general use of loops, the key difference is in the more-general approach to clock-edge usage that POCA permits. RTL code is restricted to a single clock edge per process, and the clock edge must be located at the beginning of the process.
Conversely, POCA permits as many clock edges as desired. They may be scattered throughout a process. A simple filter design coded in POCA-style Verilog uses many familiar RTL constructs (Fig. 2). The accompanying control-flow graph (CFG) has been annotated with the loop and data operations. The designer will implement this graphical view to understand the automatic micro-architecture created by architectural synthesis.
Running Synthesis: Architectural-synthesis tools are operated and controlled in much the same way as RTL synthesis tools. They can use the same technology libraries and types of timing constraints and produce the same kinds of results reports. This discussion will focus only on the differences, but most of the environment is nearly identical to that of RTL-based environments.
Architectural synthesis does "bigger" design transformations than RTL synthesis, as it's not constrained within the solution space of a single micro-architecture. The two categories of optimization transformations that architectural synthesis performs are scheduling and resource allocation.
The scheduling process assigns each operation to a clock cycle. It performs timing analysis, looks at the clock cycles and clock trees, and then distributes operations across clock cycles. If a value is crossing the cycle boundary, that will be saved in a register. To avoid multicycle operations, it splits complex operations into multiple cycles. It checks for timing violations and fixes them by rescheduling the operations.
On the other hand, the resource-allocation process decides the number and type of resources that can be used in a given implementation. It creates an FSM to control the use of these resources and generates a set of registers or memory blocks to store intermediate values. If possible, it reuses hardware resources like registers, functions, and operators.
Moreover, an architectural synthesis tool offers several capabilities not available in RTL synthesis, such as chaining, pipelining, memory inferencing, resource sharing, and register sharing. These optimization transformations are explained in many books on the subject of high-level synthesis.
In RTL-based design, the designer must perform scheduling and resource allocation tasks. With the automation provided by architectural synthesis, results of these tasks must be communicated to the designer who wants or needs to understand details of the module implementation. The most concise way to explain results is by using design abstractions, or design views, that may not be familiar to all designers. These views are the control-flow graph and data-flow graph (DFG).
One way to view a design is to look at it as consisting of three pieces of information: what, when, and where. A design is characterized by the desired behavior (what), mapped to time (when), and implemented by a specific structure (where). The DFG encapsulates the desired behavior, whereas the control-flow graph condenses timing information. During design elaboration, architectural synthesis extracts the CFG and DFG from the high-level HDL code. In the scheduling phase of architectural synthesis, the two graphs are linked and design optimizations are performed. Finally, in the allocation phase, architectural synthesis assigns hardware resources to the operations.
Architectural synthesis tools offer user interfaces that depict CFG and DFG views of the design, along with the more familiar source-code, hierarchy, and gate-level views. These views are all hyperlinked together so that their relationships can be readily understood.
The procession of steps within an architectural-synthesis tool proceeds in a generally sequential fashion, with many hidden iterations performed during various optimization steps (Fig. 3). Inputs are the POCA-style HDL code, implementation constraints, and process library (the same as used for RTL synthesis). Outputs can be generated at multiple levels of abstraction, from an optimized POCA-style scheduled design, RTL, or gate-level.