Intellectual property (ip), and its reuse, is expected to rev up soc development from conception to reality. And on paper, it does. But rarely do those selling IP cores tell you just how grueling their integration can be. System-on-a-chip (SoC) design can take much longer than one would hope, even on the second or third go-arounds with the same cores.
How can we make IP integration and reuse easier? By taking it up a notch in abstraction. And that's what Sonics Inc. has done with the Synapse 3220 addition to its portfolio of interconnect IP.
SoCs are exploding in complexity, with the number of functional blocks on a single die running up to at least 50 or more today and heading rapidly into the hundreds. Thus, a way must be found to minimize the number of objects being dealt with, and to ease the process of integration, verification, and subsequent reuse of IP.
A central connectivity issue in classical bus-based SoC architectures is the blocking transaction model, in which the interconnect is limited to servicing transactions between a processing element and peripherals one at a time. In such architectures, any other transactions are prevented from occurring until the transaction in progress is completed. The result can severely limit performance.
Take, for example, a situation in which a given SoC has multiple processors, such as a CPU core and a DSP along with other blocks that provide peripheral support. If one processor accesses a peripheral like a 32-kHz timer, it holds the bus until it receives a complete response from that timer. Many cycles could pass by before any other device can access the bus to initiate another transaction.
Stepping into this breach is Synapse 3220, an IP-based interconnect technology that addresses the overall complexity issues of SoCs. It also squarely faces the connectivity problems of systems with multiple processing elements and myriad peripherals.
The Synapse 3220 interconnect IP product is the latest in Sonics' family of SMART interconnect technologies. Launched in 1999 with the SiliconBackplane MicroNetwork IP offering, the SMART family is a plug-and-play SoC design methodology that hinges on an industry-standard socket called the Open Core Protocol (OCP).
The basic concept surrounding the OCP is that of a bus-independent interface for IP cores. The OCP can be thought of as a fully configurable "socket" that provides a standard format to develop a unique "agent" for each IP core. The resulting core-specific interface includes all of the signals required to describe the core's communications with the bus, including data flow, control, and verification and test signals. It provides a firm boundary around each core that's observable and controllable.
With the OCP as a foundation technology for defining an IP core's bus interface, a communication fabric or transport mechanism is needed. The Synapse 3220 introduction spawns a two-pronged architectural approach to that fabric. This approach brings numerous performance benefits that solve, in an elegant fashion, the issues associated with blocked bus transactions that are seen with traditional buses. It also embodies an SoC design approach that takes abstraction to the next level of hierarchy, reducing the number of objects to a level designers can grasp on a system basis.
The SiliconBackplane MicroNetwork IP product was conceived as a complete answer to the problems swirling around intercore communication on an SoC. However, SiliconBackplane is optimized to handle traffic between IP cores that are best described as "initiators," which is to say those cores that generate system traffic, and a relatively small number of IP cores that can be called "targets," or cores that are serviced by initiators. A CPU, or other processing element, is the best example of an initiator. Targets are exemplified by memories, DMAs, and off-chip communication cores, among others.
Since SiliconBackplane's introduction, though, SoC complexity—and particularly the number of targets—has skyrocketed. Synapse 3220 is the cornerstone of a divide-and-conquer strategy to manage it all (Fig. 1). It handles communication between the growing number of initiator IP cores and the even-faster-growing number of targets.
As complexity rises, Wingard sees large functional blocks being built up into a next-generation black box, or what Sonics refers to as a "tile." Think of Synapse 3220 as a generic nonblocking switch fabric aimed at connecting low-speed peripherals. "It has applications inside a tile for some of the local peripherals associated with things like booting the RTOS, as well as UARTs, timers, and others," says Wingard. "We also see Synapse 3220 being used between tiles or among tiles as a way of hooking up the I/O devices."
By virtue of its nonblocking nature, the interconnect provides low-latency access to a large number of low-bandwidth target cores that can be physically dispersed on the SoC. Many such cores can also be aggregated in a tile.
It's not as if there aren't other ways to approach the latency problems im-posed by a blocking bus structure. One alternative is to use private peripheral subsystems, or secondary buses, to interconnect a partitioned group of targets with the initiators that access them most. Such schemes can end up with buses running all over the die, eating up real estate and opening the door to signal-integrity nightmares.
Moreover, using private peripheral buses is a nonscalable and constraining approach that must be locked in during floorplanning. Any change in the SoC's functionality means a redesign for the related peripheral bus architecture.