IP Integration Is Standard Fare

The tool's graphical user interface enables designers to place network gateways, connect ports to clients, and either manually or automatically create a CHAIN topology. CHAINdesigner also generates a Verilog or SystemC description of the fabric for simulation, simulation testbenches, and constrained CHAIN netlists for input to the suite's second tool, CHAINcompiler.

That tool accepts the constrained CHAIN netlist and components from Silistix's CHAINlibrary to produce a structural netlist for inclusion in the target SoC. The structural netlist is then fed into a conventional logic-synthesis tool such as Design Compiler and mapped to standard cells. CHAINcompiler also creates scripts for static timing analysis and provides hints for placement and routing. According to Silistix, use of CHAIN interconnects results in faster SoC timing closure. No synchronous paths enter or leave the interconnect, nor do clocks, so there are no paths from arbitrary design elements. Each endpoint in the design is laid out separately.

The packet-switched network allows replacement of lower-end CPUs or DSPs with faster ones without affecting the remainder of the design. Also, the interconnect offers protocol independence and the ability to mix and match any combination of third-party or internal IP blocks supporting diverse protocols.

Further, the company claims that the interconnect reduces power both at the system and bus levels. At the system level, CHAINworks eliminates issues related to frequency balancing, because any number of unrelated clock domains can be used. This lets each IP block function at its optimal frequency rather than at some artificial derivation of a system clock, thereby consuming less power.

At the bus level, CHAIN fabrics inherently use less power than conventional synchronous buses because of the nature of self-timed circuits. Power consumption is dictated by data traffic load rather than by a clock frequency, providing automatic fine-grained power management.