Undertaking the design of a system-on-a-chip (SoC) is complex enough on its own merits. As is ever more the case, when power consumption is the primary design constraint, it becomes a task of enormous difficulty.
Over time, EDA vendors and IP providers have worked together to build an infrastructure to promote design reuse. A prime example is the collaboration between ARM and Synopsys, which yielded a Reuse Methodology Manual some years ago I (click here to check out “ARM, Synopsys Partner For SystemVerilog Verification,” at www.electronicdesign.com).
A logical next step for the collaboration was to tackle a low-power design methodology, and after 10 years of collaboration, a team of technologists from ARM and Synopsys has produced the Low Power Methodology Manual, now available from Springer. The 300-page volume begins by defining the scope of the low-power problem as pertains to SoC design and by stating its purpose, which is to describe the most effective techniques currently available for managing dynamic and static power in SoCs.
Subsequent chapters discuss various power-management techniques and approaches, including clock gating, multi-Vt design, logic-level power reduction, and multi-voltage design. Architectural issues for power gating are covered in detail, as are issues related to IP design. Dynamic voltage and frequency scaling are treated extensively as well.
Throughout the book, references are made to several low-power technology demonstration projects that the authors have used to explore low-power techniques. These include the so-called SALT project, or “Synopsys-ARM Low-power Technologhy demonstrator,” a 90-nm design consisting of an ARM processor and numerous Synopsys peripheral and I/O IP blocks.
This book is thoroughly recommended to anyone embarking on a low-power SoC project. While it may be most useful to those hewing to an ARM-based project with a Synopsys-based flow, there’s more than enough material of a generic nature to make it worthwhile for SoC designers of any stripe.