Improving Ramp-To-Volume
The emergence of sophisticated optical lithography techniques has extended designers' responsibilities in facilitating a faster ramp-to-volume. Unlike previous process generations, where manufacturing engineers could independently apply mask corrections and optimizations, sub-wavelength lithography used in nanometer processes can distort wafer-imaged structures. This will physically change design layout and alter circuit performance. Designers must anticipate these distortions before tapeout to minimize risk and reduce sensitivity to manufacturing defects.
For nanometer process technologies, particularly at 65 nm and below, the photomask shapes that represent individual on-chip geometries don't transfer accurately onto the wafer due to wavelength diffraction effects. Because the wavelength of the photoresist-exposing light source is longer than the dimensions of some structures being placed on-chip, the transferred images are distorted on the wafers themselves. Other process steps, such as etching and oxide growth, among others, exacerbate the distortion. Without corrective action, inaccurate device-image replication will lead to large yield losses.
Silicon foundries apply reticle-enhancement-technology (RET) methods to deal with diffraction-induced distortions. RET typically comprises two types of corrections: phase-shift masking (PSM) and OPC. These corrections can create smaller geometries for a given wavelength of light as well as reduce on-chip and chip-to-chip parameter variations. With PSM, the light source is split into two phases to avoid interference patterns and increase the wafer's image resolution.
OPC compensates for line shortening, corner rounding, and other distortions caused by features smaller than the wavelength of the exposing light. Here, the OPC technique augments the mask image with additional features that are smaller than the nominal mask design rules. OPC is typically required for more than two-thirds of the layers for 130-nm designs and virtually all layers at 90 nm. Because the added OPC features are smaller than the nominal mask design rules, these features are much more difficult to generate and process. Consequently, indiscriminately using OPC adds significant complexity to the physical database, dramatically increasing tool run-time and delaying time-to-volume.
By adding new lithography-aware tools in design chains, designers can more efficiently account for subwavelength lithographic effects. As engineers design individual cells, these tools can quickly identify where potential problems may later arise in PSM or OPC. Furthermore, passing along information about critical design structures to lithography helps engineers focus OPC to specific regions of a design as well as reduce OPC run times. As these tools move further upstream in the design chain, semiconductor companies will be able to minimize OPC requirements to produce masks of the lowest possible complexity-reducing costs while maximizing device performance and die yield.
Volume Production
In classic development models, yield improvement relies on detailed process analysis and manufacturing diagnosis. Here, engineers carefully monitor the process to determine if it's within nominal specifications, and the foundry fine-tunes the process to the design to achieve maximum yield.
Advanced process-monitoring software arms engineers with a diagnostic environment that lets them more effectively analyze design intent and collate manufacturing information to develop better yield-enhancement solutions. Engineers also may use special failure-analysis equipment to isolate root causes of chip failures, thereby identifying any yield-affecting problems in the chip-fabrication process.
Each yield enhancement in this stage directly contributes to greater profitability, so the ability to achieve maximum yield early in volume production will continue to provide a significant advantage. As a result, semiconductor companies likely will adopt emerging capabilities that tighten the data flow between the factory floor and the design station. By improving the ability to anticipate yield improvements earlier in design, semiconductor companies will achieve maximum profitability for even the most complex nanometer designs.
Enhancing Yield In Design
Nanometer yield enhancement requires a more collaborative approach that involves all participants in the design chain: designers, IP vendors, tool providers, and foundries. Instead of tuning a manufacturing process to each design, semiconductor companies and foundries will need to collaborate more actively to tune each design to the process. In turn, success in nanometer design depends on the ability to deploy a design chain that's attuned to the manufacturing requirements of each specific design.
Indeed, every aspect of product development has an impact on yield. By deploying manufacturing-aware tools and methods early in development, semiconductor companies can anticipate potential problems well before silicon. By addressing yield early and often throughout design, semiconductor companies can achieve faster ramp-to-volume production and profit for complex nanometer designs.
Improving Ramp-To-Volume
The emergence of sophisticated optical lithography techniques has extended designers' responsibilities in facilitating a faster ramp-to-volume. Unlike previous process generations, where manufacturing engineers could independently apply mask corrections and optimizations, sub-wavelength lithography used in nanometer processes can distort wafer-imaged structures. This will physically change design layout and alter circuit performance. Designers must anticipate these distortions before tapeout to minimize risk and reduce sensitivity to manufacturing defects.
For nanometer process technologies, particularly at 65 nm and below, the photomask shapes that represent individual on-chip geometries don't transfer accurately onto the wafer due to wavelength diffraction effects. Because the wavelength of the photoresist-exposing light source is longer than the dimensions of some structures being placed on-chip, the transferred images are distorted on the wafers themselves. Other process steps, such as etching and oxide growth, among others, exacerbate the distortion. Without corrective action, inaccurate device-image replication will lead to large yield losses.
Silicon foundries apply reticle-enhancement-technology (RET) methods to deal with diffraction-induced distortions. RET typically comprises two types of corrections: phase-shift masking (PSM) and OPC. These corrections can create smaller geometries for a given wavelength of light as well as reduce on-chip and chip-to-chip parameter variations. With PSM, the light source is split into two phases to avoid interference patterns and increase the wafer's image resolution.
OPC compensates for line shortening, corner rounding, and other distortions caused by features smaller than the wavelength of the exposing light. Here, the OPC technique augments the mask image with additional features that are smaller than the nominal mask design rules. OPC is typically required for more than two-thirds of the layers for 130-nm designs and virtually all layers at 90 nm. Because the added OPC features are smaller than the nominal mask design rules, these features are much more difficult to generate and process. Consequently, indiscriminately using OPC adds significant complexity to the physical database, dramatically increasing tool run-time and delaying time-to-volume.
By adding new lithography-aware tools in design chains, designers can more efficiently account for subwavelength lithographic effects. As engineers design individual cells, these tools can quickly identify where potential problems may later arise in PSM or OPC. Furthermore, passing along information about critical design structures to lithography helps engineers focus OPC to specific regions of a design as well as reduce OPC run times. As these tools move further upstream in the design chain, semiconductor companies will be able to minimize OPC requirements to produce masks of the lowest possible complexity-reducing costs while maximizing device performance and die yield.
Volume Production
In classic development models, yield improvement relies on detailed process analysis and manufacturing diagnosis. Here, engineers carefully monitor the process to determine if it's within nominal specifications, and the foundry fine-tunes the process to the design to achieve maximum yield.
Advanced process-monitoring software arms engineers with a diagnostic environment that lets them more effectively analyze design intent and collate manufacturing information to develop better yield-enhancement solutions. Engineers also may use special failure-analysis equipment to isolate root causes of chip failures, thereby identifying any yield-affecting problems in the chip-fabrication process.
Each yield enhancement in this stage directly contributes to greater profitability, so the ability to achieve maximum yield early in volume production will continue to provide a significant advantage. As a result, semiconductor companies likely will adopt emerging capabilities that tighten the data flow between the factory floor and the design station. By improving the ability to anticipate yield improvements earlier in design, semiconductor companies will achieve maximum profitability for even the most complex nanometer designs.
Enhancing Yield In Design
Nanometer yield enhancement requires a more collaborative approach that involves all participants in the design chain: designers, IP vendors, tool providers, and foundries. Instead of tuning a manufacturing process to each design, semiconductor companies and foundries will need to collaborate more actively to tune each design to the process. In turn, success in nanometer design depends on the ability to deploy a design chain that's attuned to the manufacturing requirements of each specific design.
Indeed, every aspect of product development has an impact on yield. By deploying manufacturing-aware tools and methods early in development, semiconductor companies can anticipate potential problems well before silicon. By addressing yield early and often throughout design, semiconductor companies can achieve faster ramp-to-volume production and profit for complex nanometer designs.