The key issue now is how to predict and optimize the design of power planes. Without a good design-and-analysis methodology, one of two outcomes may occur. Power planes may respond inadequately, thereby increasing common-mode EMI that can radiate from cables and possibly cause system failure. Or, the decoupling system may end up being over-designed,
driving up system cost unnecessarily.
Traditional SI simulation approaches have concentrated on modeling circuit behavior in the time domain. This is true of almost all current SI- and crosstalk-analysis tools. An SI analysis typically assumes that the behavior of the pc-board power and ground planes is ideal. To accurately predict the effect of the PDS response, the traditional circuit model must be augmented with a power-distribution model. The combined response of the device output and the PDS is then analyzed.
This is a good example of a "verification-based" approach. It emphasizes accuracy over speed, requiring a lengthy analysis to predict the detailed behavior of a single set of outputs. But this type of analysis is not conducive to the design process, where the designer wants to create an initial configuration, run a quick simulation, and then make adjustments to the design, based on the results of the analysis. What's more, lengthy, time-domain analysis can validate the behavior of only a single driver output, and there are thousands of them in an average pc board.
Another significant problem is that time-domain analysis assumes that the demand for instantaneous current is driven by the I/O ring, rather than by the device core. For devices that have a "standby" low-power mode and can "wake up" in a single cycle, this is a grossly optimistic assumption. The peak demand for power will occur during device wakeup, and time-domain analysis of output switching behavior simply won't predict this.
A new and different approach is to analyze the behavior of the PDS by itself in the frequency domain. If the maximum instantaneous current and permissible PDS voltage drop are known, then the maximum allowable PDS impedance can be determined simply from Ohm's law. For all frequencies with significant currents, the PDS must present an impedance equal to or less than the target impedance. The goal is still to design a PDS that "meets or beats" the target impedance at all points on the pc board. But the analysis strategy changes considerably.
The power and ground planes can be represented as a distributed electrical circuit. This can be illustrated as a matrix of R, L, G, and C values, or better yet by a transmission-line mesh. The pow-er/ground planes are meshed and converted into a network of nodes that represent the distributed behavior of the planes. Bulk and decoupling capacitors are represented by their bulk capacitance as well as their parasitic inductive and resistive values. They're then connected to the appropriate nodes in the mesh. Voltage and noise sources can be connected to the mesh to model the behavior of supplies and the devices, creating demands for instantaneous current.
Once the PDS model is created, it can be analyzed in the frequency domain, thereby determining the impedance of each node over the frequency range of interest. The transimpedance value for each node in the mesh represents the frequency-dependent PDS impedance that a device would see if its power pin were attached to the power or ground plane at that point. This can be analyzed and plotted to determine if the PDS meets the target requirements. Any problem areas in the design can be identified and the design can be changed, repeating the process until satisfactory performance is achieved. This methodology critically depends on several factors:
- Accurate modeling of capacitor parasitics. Values are obtained from precision measurements. Fortunately, practical experience has demonstrated that parasitics can be estimated if the capacitor material technology and dimensions are known.
- Accurate modeling of decoupling-capacitor loop inductance. Loop inductance is a primary factor in determining the upper frequency limit of a capacitor's effectiveness. 3D field solvers are used to model the device's connection to the power planes and determine the loop inductance.
- Accurate modeling of the power plane parasitic values. This also is well suited to 2D and 3D field solutions.
- Fast and accurate frequency-domain analysis of the combined structure.
The design process just described can be performed using a standard netlist-driven analysis approach. But the task of changing the values and location of capacitors would become incredibly difficult. The job of correlating the simulation results versus the regions in the pc-board layout would become tougher as well.
Therefore, integration with a graphical pc-board design tool is preferable. This way the user can place devices graphically in the pc-board layout and then quickly correlate simulation results with regions of the pc board for debugging. Integration with the pc-board design tool simplifies the design process, speeds iterations, and greatly reduces the overall chance of error.